TY - GEN
T1 - GPU-RANC
T2 - 2024 IEEE Neuro Inspired Computational Elements Conference, NICE 2024
AU - Hassan, Sahil
AU - Inouye, Michael
AU - Gonzalez, Miguel C.
AU - Aliyev, Ilkin
AU - Mack, Joshua
AU - Hafiz, Maisha
AU - Akoglu, Ali
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Open-source simulation tools play a crucial role for neuromorphic application engineers and hardware architects to investigate performance bottlenecks and explore design optimizations before committing to silicon. Reconfigurable Architecture for Neuromorphic Computing (RANC) is one such tool that offers ability to execute pre-Trained Spiking Neural Network (SNN) models within a unified ecosystem through both software-based simulation and FPGA-based emulation. RANC has been utilized by the community with its flexible and highly parameterized design to study implementation bottlenecks, tune architectural parameters or modify neuron behavior based on application insights and study the trade space on hardware performance and network accuracy. In designing architectures for use in neuromorphic computing, there are an incredibly large number of configuration parameters such as number and precision of weights per neuron, neuron and axon counts per core, network topology, and neuron behavior. To accelerate such studies and provide users with a streamlined productive design space exploration, in this paper we introduce the GPU-based implementation of RANC. We summarize our parallelization approach and quantify the speedup gains achieved with GPU-based tick-Accurate simulations across various use cases. We demonstrate up to 780 times speedup compared to serial version of the RANC simulator based on a 512 neuromorphic core MNIST inference application. We believe that the RANC ecosystem now provides a much more feasible avenue in the research of exploring different optimizations for accelerating SNNs and performing richer studies by enabling rapid convergence to optimized neuromorphic architectures.
AB - Open-source simulation tools play a crucial role for neuromorphic application engineers and hardware architects to investigate performance bottlenecks and explore design optimizations before committing to silicon. Reconfigurable Architecture for Neuromorphic Computing (RANC) is one such tool that offers ability to execute pre-Trained Spiking Neural Network (SNN) models within a unified ecosystem through both software-based simulation and FPGA-based emulation. RANC has been utilized by the community with its flexible and highly parameterized design to study implementation bottlenecks, tune architectural parameters or modify neuron behavior based on application insights and study the trade space on hardware performance and network accuracy. In designing architectures for use in neuromorphic computing, there are an incredibly large number of configuration parameters such as number and precision of weights per neuron, neuron and axon counts per core, network topology, and neuron behavior. To accelerate such studies and provide users with a streamlined productive design space exploration, in this paper we introduce the GPU-based implementation of RANC. We summarize our parallelization approach and quantify the speedup gains achieved with GPU-based tick-Accurate simulations across various use cases. We demonstrate up to 780 times speedup compared to serial version of the RANC simulator based on a 512 neuromorphic core MNIST inference application. We believe that the RANC ecosystem now provides a much more feasible avenue in the research of exploring different optimizations for accelerating SNNs and performing richer studies by enabling rapid convergence to optimized neuromorphic architectures.
KW - CUDA
KW - Graphics Processing Unit (GPU)
KW - Neuromorphic computing
KW - Spiking Neural Network (SNN)
UR - http://www.scopus.com/inward/record.url?scp=85196731128&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85196731128&partnerID=8YFLogxK
U2 - 10.1109/NICE61972.2024.10548776
DO - 10.1109/NICE61972.2024.10548776
M3 - Conference contribution
AN - SCOPUS:85196731128
T3 - 2024 IEEE Neuro Inspired Computational Elements Conference, NICE 2024 - Proceedings
BT - 2024 IEEE Neuro Inspired Computational Elements Conference, NICE 2024 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 23 April 2024 through 26 April 2024
ER -