FPGA implementation of high performance QC-LDPC decoder for optical communications

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations


Forward error correction is as one of the key technologies enabling the next-generation high-speed fiber optical communications. Quasi-cyclic (QC) low-density parity-check (LDPC) codes have been considered as one of the promising candidates due to their large coding gain performance and low implementation complexity. In this paper, we present our designed QC-LDPC code with girth 10 and 25% overhead based on pairwise balanced design. By FPGAbased emulation, we demonstrate that the 5-bit soft-decision LDPC decoder can achieve 11.8dB net coding gain with no error floor at BER of 10-15avoiding using any outer code or post-processing method. We believe that the proposed single QC-LDPC code is a promising solution for 400Gb/s optical communication systems and beyond.

Original languageEnglish (US)
Title of host publicationOptical Metro Networks and Short-Haul Systems VII
EditorsAtul K. Srivastava, Benjamin B. Dingel, Achyut K. Dutta
ISBN (Electronic)9781628414783
StatePublished - 2015
EventOptical Metro Networks and Short-Haul Systems VII - San Francisco, United States
Duration: Feb 10 2015Feb 12 2015

Publication series

NameProceedings of SPIE - The International Society for Optical Engineering
ISSN (Print)0277-786X
ISSN (Electronic)1996-756X


OtherOptical Metro Networks and Short-Haul Systems VII
Country/TerritoryUnited States
CitySan Francisco


  • Fiber-optics communications
  • Low-density parity-check (LDPC) codes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Computer Science Applications
  • Applied Mathematics
  • Electrical and Electronic Engineering


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