TY - GEN
T1 - FPGA-based high-speed authenticated encryption system
AU - Muehlberghuber, Michael
AU - Keller, Christoph
AU - Gürkaynak, Frank K.
AU - Felber, Norbert
N1 - Publisher Copyright:
© IFIP International Federation for Information Proessing 2013.
PY - 2013
Y1 - 2013
N2 - The Advanced Encryption Standard (AES) running in the Galois/Counter Mode of Operation represents a de facto standard in the field of hardware-accelerated, block-cipher-based high-speed authenticated encryption (AE) systems. We propose hardware architectures supporting the Ethernet standard IEEE 802.3ba utilizing different cryptographic primitives suitable for AE applications. Our main design goal was to achieve high throughput on FPGA platforms. Compared to previous works aiming at data rates beyond 100 Gbit/s, our design makes use of an alternative block cipher and an alternative mode of operation, namely Serpent and the offset codebook mode of operation, respectively. Using four cipher cores for the encryption part of the AE architecture, we achieve a throughput of 141 Gbit/s on an Altera Stratix IV FPGA. The design requires 39 kALMs and runs at a maximum clock frequency of 275 MHz. This represents, to the best of our knowledge, the fastest full implementation of an AE scheme on FPGAs to date. In order to make the design applicable in a real-world environment, we developed a custom-designed printed circuit board for the Stratix IV FPGA, suitable to process data with up to 100 Gbit/s.
AB - The Advanced Encryption Standard (AES) running in the Galois/Counter Mode of Operation represents a de facto standard in the field of hardware-accelerated, block-cipher-based high-speed authenticated encryption (AE) systems. We propose hardware architectures supporting the Ethernet standard IEEE 802.3ba utilizing different cryptographic primitives suitable for AE applications. Our main design goal was to achieve high throughput on FPGA platforms. Compared to previous works aiming at data rates beyond 100 Gbit/s, our design makes use of an alternative block cipher and an alternative mode of operation, namely Serpent and the offset codebook mode of operation, respectively. Using four cipher cores for the encryption part of the AE architecture, we achieve a throughput of 141 Gbit/s on an Altera Stratix IV FPGA. The design requires 39 kALMs and runs at a maximum clock frequency of 275 MHz. This represents, to the best of our knowledge, the fastest full implementation of an AE scheme on FPGAs to date. In order to make the design applicable in a real-world environment, we developed a custom-designed printed circuit board for the Stratix IV FPGA, suitable to process data with up to 100 Gbit/s.
KW - AES
KW - Authenticated encryption
KW - FPGA
KW - GCM
KW - High-throughput architecture
KW - OCB
KW - Pipelining
KW - Serpent
UR - http://www.scopus.com/inward/record.url?scp=85025163979&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85025163979&partnerID=8YFLogxK
U2 - 10.1007/978-3-642-45073-0_1
DO - 10.1007/978-3-642-45073-0_1
M3 - Conference contribution
AN - SCOPUS:85025163979
SN - 9783642450723
T3 - IFIP Advances in Information and Communication Technology
SP - 1
EP - 20
BT - VLSI-SoC
A2 - Katkoori, Srinivas
A2 - Reis, Ricardo
A2 - Guthaus, Matthew R.
A2 - Burg, Andreas
A2 - Coskun, Ayse
A2 - Guthaus, Matthew
A2 - Reis, Ricardo
A2 - Katkoori, Srinivas
A2 - Burg, Andreas
A2 - Coskun, Ayse
PB - Springer New York LLC
T2 - 20th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012
Y2 - 7 October 2012 through 10 October 2012
ER -