TY - GEN
T1 - Fault tolerant memories based on expander graphs
AU - Chilappagari, Shashi Kiran
AU - Vasić, Bane
PY - 2007
Y1 - 2007
N2 - In this paper we consider memories built from components subject to transient faults. We propose a fault-tolerant memory architecture based on LDPC codes and show the existence of memories which can tolerate constant fraction of failures in all the components. Our proof relies on the expansion property of the underlying Tanner graph of the code. We illustrate our results with specific numerical examples.
AB - In this paper we consider memories built from components subject to transient faults. We propose a fault-tolerant memory architecture based on LDPC codes and show the existence of memories which can tolerate constant fraction of failures in all the components. Our proof relies on the expansion property of the underlying Tanner graph of the code. We illustrate our results with specific numerical examples.
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U2 - 10.1109/ITW.2007.4313061
DO - 10.1109/ITW.2007.4313061
M3 - Conference contribution
AN - SCOPUS:46749111147
SN - 1424415640
SN - 9781424415649
T3 - 2007 IEEE Information Theory Workshop, ITW 2007, Proceedings
SP - 126
EP - 131
BT - 2007 IEEE Information Theory Workshop, ITW 2007, Proceedings
T2 - 2007 IEEE Information Theory Workshop, ITW 2007
Y2 - 2 September 2007 through 6 September 2007
ER -