Abstract
We introduce a new approach to automatically extract an idealized logical structure from a parallel execution trace. We use this structure to define intuitive metrics such as the lateness of a process involved in a parallel execution. By analyzing and illustrating traces in terms of logical steps, we leverage a developer's understanding of the happened-before relations in a parallel program. This technique can uncover dependency chains, elucidate communication patterns, and highlight sources and propagation of delays, all of which may be obscured in a traditional trace visualization.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 397-398 |
| Number of pages | 2 |
| Journal | ACM SIGPLAN Notices |
| Volume | 49 |
| Issue number | 8 |
| DOIs | |
| State | Published - Aug 2014 |
| Externally published | Yes |
Keywords
- Logical structure
- Parallel execution trace
- Visualization
ASJC Scopus subject areas
- General Computer Science