TY - GEN
T1 - Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects
AU - Morris, Randy
AU - Kodi, Avinash
AU - Louri, Ahmed
PY - 2013
Y1 - 2013
N2 - As we integrate hundreds of cores in the future, energy-efficiency and scalability of Network-on-Chips (NoCs) has become a critical challenge. In order to achieve higher performance-per-Watt than traditional metallic interconnects, researchers are exploring alternate energy-effident emerging technology solutions. In this paper, we propose to combine two emerging technologies, namely 3D stacking and nanophotonics that can deliver high on-chip bandwidth and low energy/bit to achieve a high-throughput, reconfigurable and scalable NoC for many-core systems. Our simulation results indicate that the execution time can be reduced up to 25% and energy consumption reduced by 23% for Splash-2, PARSEC, SPEC CPU2006 and synthetic benchmarks for 64-core and 256-core versions.
AB - As we integrate hundreds of cores in the future, energy-efficiency and scalability of Network-on-Chips (NoCs) has become a critical challenge. In order to achieve higher performance-per-Watt than traditional metallic interconnects, researchers are exploring alternate energy-effident emerging technology solutions. In this paper, we propose to combine two emerging technologies, namely 3D stacking and nanophotonics that can deliver high on-chip bandwidth and low energy/bit to achieve a high-throughput, reconfigurable and scalable NoC for many-core systems. Our simulation results indicate that the execution time can be reduced up to 25% and energy consumption reduced by 23% for Splash-2, PARSEC, SPEC CPU2006 and synthetic benchmarks for 64-core and 256-core versions.
KW - Nanophotonics
KW - NoCs
KW - Reconfiguration
UR - http://www.scopus.com/inward/record.url?scp=84893427301&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84893427301&partnerID=8YFLogxK
U2 - 10.1109/SLIP.2013.6681676
DO - 10.1109/SLIP.2013.6681676
M3 - Conference contribution
AN - SCOPUS:84893427301
SN - 9781467361736
T3 - International Workshop on System Level Interconnect Prediction, SLIP
BT - 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
PB - Association for Computing Machinery
T2 - 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013
Y2 - 2 June 2013 through 2 June 2013
ER -