Evaluating Embedded Hardware for High-order Wavefront Sensing and Control

Future space telescopes such as the Habitable Worlds Observatory (HWO) will use coronagraphs and wavefront control to achieve the ∼ 10⁻¹⁰ contrast necessary to directly image Earth-like exoplanets. Wavefront control algorithms such as Electric Field Conjugation (EFC) will control thousands of actuators at cadences of seconds or minutes. EFC uses a Jacobian matrix which maps deformable-mirror (DM) voltages to the change in electric field at the image plane. The Jacobian matrix grows in size with the number of pixels, DM actuators, and spectral channels. EFC on proposed future telescopes like HabEx and LUVOIR will require as much as 25 GFLOPS (floating point operations per second). This level of compute density has never been achieved on radiation-hardened processors that are used on NASA Class-A missions such as the Roman Space Telescope. Previous work has focused on estimating the compute density (CD) of processors using assumptions about memory access characteristics and the parallelizability of algorithm implementation. Such analysis produces large uncertainty due to the assumptions necessary to compute CD. To refine the estimates of EFC compute capability of current generation processors, we determine the FLOPS performance of processors using benchmark tests which represent the operations mix and memory access patterns of EFC. The expected EFC iteration computation period on future space telescopes based on application benchmarks is reported. We additionally discuss plans for processor-in-the-loop testing with a characteristic optical model. We have created a ray tracing optical model for the telescope assembly as well as a physical optics model for the telescope and coronagraph for the purposes of testing HOWFC algorithms. This testing can be applied to CPUs and FPGAs, representing a range of potential compute architectures.