Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design

Kyle Kuan, Tosiron Adegbija

Research output: Contribution to journalArticlepeer-review

18 Scopus citations


Much research has shown that applications have variable runtime cache requirements. In the context of the increasingly popular spin-transfer torque RAM (STT-RAM) cache, the retention time, which defines how long the cache can retain a cache block in the absence of power, is one of the most important cache requirements that may vary for different applications. In this paper, we propose a logically adaptable retention time STT-RAM (LARS) cache that allows the retention time to be dynamically adapted to applications' runtime requirements. LARS cache comprises of multiple STT-RAM units with different retention times, with only one unit being used at a given time. LARS dynamically determines which STT-RAM unit to use during runtime, based on executing applications' needs. As an integral part of LARS, we also explore different algorithms to dynamically determine the best retention time based on different cache design tradeoffs. Our experiments show that by adapting the retention time to different applications' requirements, LARS cache can reduce the average cache energy by 25.31%, compared to prior work, with minimal overheads.

Original languageEnglish (US)
Article number8695746
Pages (from-to)1328-1339
Number of pages12
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number6
StatePublished - Jun 2020


  • Adaptable hardware
  • configurable memory
  • low-power embedded systems
  • retention time
  • spin-transfer torque RAM (STT-RAM) cache

ASJC Scopus subject areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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