TY - GEN
T1 - Energy and performance analysis of sttram caches for mobile applications
AU - Kuan, Kyle
AU - Adegbija, Tosiron
N1 - Funding Information:
This work was supported in part by NSF Grant CAREER 1844952.
Publisher Copyright:
© 2019 IEEE.
PY - 2019/10
Y1 - 2019/10
N2 - Spin-Transfer Torque RAMs (STTRAMs) have been shown to offer much promise for implementing emerging cache architectures. This paper studies the viability of STTRAM caches for mobile workloads from the perspective of energy and latency. Specifically, we explore the benefits of reduced retention STTRAM caches for mobile applications. We analyze the characteristics of mobile applications' cache blocks and how those characteristics dictate the appropriate retention time for mobile device caches. We show that due to their inherently interactive nature, mobile applications' execution characteristics-and hence, STTRAM cache design requirements-differ from other kinds of applications. We also explore various STTRAM cache designs in both single and multicore systems, and at different cache levels, that can efficiently satisfy mobile applications' execution requirements, in order to maximize energy savings without introducing substantial latency overhead.
AB - Spin-Transfer Torque RAMs (STTRAMs) have been shown to offer much promise for implementing emerging cache architectures. This paper studies the viability of STTRAM caches for mobile workloads from the perspective of energy and latency. Specifically, we explore the benefits of reduced retention STTRAM caches for mobile applications. We analyze the characteristics of mobile applications' cache blocks and how those characteristics dictate the appropriate retention time for mobile device caches. We show that due to their inherently interactive nature, mobile applications' execution characteristics-and hence, STTRAM cache design requirements-differ from other kinds of applications. We also explore various STTRAM cache designs in both single and multicore systems, and at different cache levels, that can efficiently satisfy mobile applications' execution requirements, in order to maximize energy savings without introducing substantial latency overhead.
KW - Energy efficient
KW - Mobile applications
KW - Multicore processor
KW - Non volatile memory
KW - Performance analysis
KW - Retention time
KW - Spin-Transfer Torque RAM (STTRAM) cache
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U2 - 10.1109/MCSoC.2019.00044
DO - 10.1109/MCSoC.2019.00044
M3 - Conference contribution
AN - SCOPUS:85076138465
T3 - Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
SP - 257
EP - 264
BT - Proceedings - 2019 IEEE 13th International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 13th IEEE International Symposium on Embedded Multicore/Many-Core Systems-on-Chip, MCSoC 2019
Y2 - 1 October 2019 through 4 October 2019
ER -