Enabling right-provisioned microprocessor architectures for the internet of things

The Internet of Things (IoT) consists of embedded low-power devices that collect and transmit data to centralized head nodes that process and analyze the data, and drive actions. The proliferation of these connected low-power devices will result in a data explosion that will significantly increase data transmission costs with respect to energy consumed and latency. Edge computing performs computations at the edge nodes prior to data transmission to interpret and/or utilize the data, thus reducing transmission costs. In this work, we seek to understand the interactions between IoT applications' execution characteristics (e.g., compute/memory intensity, cache miss rates, etc.) and the edge nodes' microarchitectural characteristics (e.g., clock frequency, memory capacity, etc.) for efficient and effective edge computing. Thus, we present a broad and tractable IoT application classification methodology and using this classification, we analyze the microarchitectural characteristics of a wide range of state-of-the - Art embedded system microprocessors and evaluate the microprocessors' applicability to IoT computation using various evaluation metrics. We also investigate and quantify the impact of leakage power reduction on the overall energy consumption across different architectures. Our work provides insights into the microarchitectural characteristics' impact on system performance and efficiency for various IoT application requirements. Our work also provides a foundation for the analysis and design of a diverse set of microprocessor architectures for IoT edge computing.