TY - JOUR
T1 - Electrical Packaging Impact on Source Components in Optical Interconnects
AU - Neifeld, Mark A.
AU - Chou, Wu Chun
N1 - Funding Information:
work was supported by the Semiconductor Research Corporation under contract 93MJ321.
PY - 1995/8
Y1 - 1995/8
N2 - A simulation study of source module components for use within optical interconnect systems is described. SPICE models of laser diodes, CMOS drivers, and electrical packages are developed and exercised to evaluate overall source module performance. Performance metrics for power dissipation, signal latency, wavelength chirp, and signal fidelity are used, The effects of laser diode threshold current, bias condition, and driving current level are determined with respect to these metrics. The influence of driver type and electrical packaging technologies on source module performance is also evaluated. Transmission line models of printed wiring board (PWB), tape automated bonding (TAB), and flip-chip bonding (C4) are used to study package related effects. It is found that under appropriate operating conditions, PWB can achieve acceptable noise, power, and latency performance for data rates up to 500 MHz while flip-chip bonding is required to exceed data rates of 800 MHz for the cases studied.
AB - A simulation study of source module components for use within optical interconnect systems is described. SPICE models of laser diodes, CMOS drivers, and electrical packages are developed and exercised to evaluate overall source module performance. Performance metrics for power dissipation, signal latency, wavelength chirp, and signal fidelity are used, The effects of laser diode threshold current, bias condition, and driving current level are determined with respect to these metrics. The influence of driver type and electrical packaging technologies on source module performance is also evaluated. Transmission line models of printed wiring board (PWB), tape automated bonding (TAB), and flip-chip bonding (C4) are used to study package related effects. It is found that under appropriate operating conditions, PWB can achieve acceptable noise, power, and latency performance for data rates up to 500 MHz while flip-chip bonding is required to exceed data rates of 800 MHz for the cases studied.
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U2 - 10.1109/96.404119
DO - 10.1109/96.404119
M3 - Article
AN - SCOPUS:0029359698
SN - 1070-9894
VL - 18
SP - 578
EP - 595
JO - IEEE Transactions on Components Packaging and Manufacturing Technology Part B
JF - IEEE Transactions on Components Packaging and Manufacturing Technology Part B
IS - 3
ER -