Efficient realization of probabilistic gradient descent bit flipping decoders

Khoa Le, David Declercq, Fakhreddine Ghaffari, Christian Spagnol, Emmanuel Popovici, Predrag Ivanis, Bane Vasic

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

In this paper, several implementations of the recently introduced PGDBF decoder for LDPC codes are proposed. In [2], the authors show that using randomness in bit-flipping decoders can greatly improve the error correction performance. In this paper, two models of random generators are proposed and compared through hardware implementation and performance simulation. A conventional implementation of the random generator through LFSR as a first design, and a new approach using binary sequences that are produced by the LDPC decoder, named IVRG, as second design. We show that both implementation of the PGDBF improve greatly the error correction performance, while maintaining the same large throughtput. However, the performance gain requires a large hardware overhead in the case of LFSR-PGDBF, while the overhead is limited to only 10% in the case of the IVRG-PGDBF.

Original languageEnglish (US)
Title of host publication2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1494-1497
Number of pages4
ISBN (Electronic)9781479983919
DOIs
StatePublished - Jul 27 2015
EventIEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
Duration: May 24 2015May 27 2015

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2015-July
ISSN (Print)0271-4310

Other

OtherIEEE International Symposium on Circuits and Systems, ISCAS 2015
Country/TerritoryPortugal
CityLisbon
Period5/24/155/27/15

Keywords

  • LDPC decoders
  • PGDBF
  • bit-flipping
  • random generators

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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