TY - GEN
T1 - Efficient FPGA implementation of probabilistic gallager B LDPC decoder
AU - Ghaffari, Fakhreddine
AU - Unal, Burak
AU - Akoglu, Ali
AU - Le, Khoa
AU - Declercq, David
AU - Vasic, Bane
N1 - Funding Information:
This work was supported by the National Science Foundation under Grant ECCS-1500170 and CCF-1314147, the Indo-US Science and Technology Forum (IUSSTF) through the Joint Networked Center for Data Storage Research (JC-16-2014-US), and the French ANR project NAND under grant agreement ANR-15CE25-0006-01.
Publisher Copyright:
© 2017 IEEE.
PY - 2017/7/2
Y1 - 2017/7/2
N2 - This paper presents the performance evaluation of the Probabilistic Gallager B (PGaB), a hard decision message passing Low Density Parity Check (LDPC) Decoder, with respect to the soft decision based decoders MinSum (MS) and Offset-MinSum (OMS). PGaB algorithm relies on introducing deliberate and controlled randomness to some of the exchanged messages of the GaB decoder such that it is able to escape from local minima associated with dominant trapping sets. We show that PGaB delivers higher decoding throughput than soft decision based decoders MS and OMS while using much fewer amount of Field Programmable Gate Array (FPGA) resources. Our Monte-Carlo simulation results show that the decoding performance of the PGaB on Binary Symmetric Channel (BSC) is far better than the deterministic GaB and very close to MS and OMS performances especially in error floor region.
AB - This paper presents the performance evaluation of the Probabilistic Gallager B (PGaB), a hard decision message passing Low Density Parity Check (LDPC) Decoder, with respect to the soft decision based decoders MinSum (MS) and Offset-MinSum (OMS). PGaB algorithm relies on introducing deliberate and controlled randomness to some of the exchanged messages of the GaB decoder such that it is able to escape from local minima associated with dominant trapping sets. We show that PGaB delivers higher decoding throughput than soft decision based decoders MS and OMS while using much fewer amount of Field Programmable Gate Array (FPGA) resources. Our Monte-Carlo simulation results show that the decoding performance of the PGaB on Binary Symmetric Channel (BSC) is far better than the deterministic GaB and very close to MS and OMS performances especially in error floor region.
KW - FPGA architecture
KW - hardware complexity/decoding performance trade-off
KW - high-performance probabilistic hard-decision LDPC decoders
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U2 - 10.1109/ICECS.2017.8292048
DO - 10.1109/ICECS.2017.8292048
M3 - Conference contribution
AN - SCOPUS:85047259829
T3 - ICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems
SP - 178
EP - 181
BT - ICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017
Y2 - 5 December 2017 through 8 December 2017
ER -