TY - GEN
T1 - Early assessment of leakage power for system level design
AU - Talarico, C.
AU - Pillilli, B.
AU - Vakati, K. L.
AU - Wang, J. M.
PY - 2005
Y1 - 2005
N2 - This paper presents a system level methodology for analyzing leakage power in the early stages of a system design. The assessment of leakage takes into account the simultaneous effect of threshold-voltage (Vt), oxide thickness (t/sub ox/), device width (W), the inputs applied and statistical process variations. The approach has been validated by applying it to the design of a digital signal processing system. The results indicate that our power estimation technique is within 10% of SPICE, with the benefit of executing 15/spl times/ faster.
AB - This paper presents a system level methodology for analyzing leakage power in the early stages of a system design. The assessment of leakage takes into account the simultaneous effect of threshold-voltage (Vt), oxide thickness (t/sub ox/), device width (W), the inputs applied and statistical process variations. The approach has been validated by applying it to the design of a digital signal processing system. The results indicate that our power estimation technique is within 10% of SPICE, with the benefit of executing 15/spl times/ faster.
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U2 - 10.1109/ISQED.2005.50
DO - 10.1109/ISQED.2005.50
M3 - Conference contribution
AN - SCOPUS:84886662558
SN - 0769523013
SN - 9780769523019
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 133
EP - 136
BT - Proceedings - 6th International Symposium on Quality Electronic Design, ISQED 2005
T2 - 6th International Symposium on Quality Electronic Design, ISQED 2005
Y2 - 21 March 2005 through 23 March 2005
ER -