Designing Constant-Timed Accelerators using High-Level Synthesis: A Case Study of ECG Biometric Authentication

James Kuban; Tosiron Adegbija

doi:10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134115

Designing Constant-Timed Accelerators using High-Level Synthesis: A Case Study of ECG Biometric Authentication

James Kuban, Tosiron Adegbija

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

High-level synthesis (HLS) is an increasingly popular approach for rapidly designing complex, high-performance, and energy-efficient application-specific accelerators, enabling a shorter time to market and increased productivity. This paper explores a workflow for generating constant-timed accelerators using generic HLS tools in order to eliminate the timing-based side-channel vulnerabilities intrinsic to accelerators generated using state-of-the-art HLS. Since security, performance, and energy are often conflicting design objectives, we also explore ways to mitigate the design overhead. We demonstrate the workflow using a case study of an ECG biometric authentication system, which exemplifies a real-world system with significant timing side-channel vulnerabilities. Results show that the workflow successfully generates constant-timed accelerators and enables designers to use generic HLS tools, thereby minimizing any negative impacts on the design process.

Original language	English (US)
Title of host publication	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350334166
DOIs	https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134115
State	Published - 2023
Externally published	Yes
Event	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Hsinchu, Taiwan, Province of China Duration: Apr 17 2023 → Apr 20 2023

Publication series

Name	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

Conference

Conference	2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	4/17/23 → 4/20/23

ASJC Scopus subject areas

Artificial Intelligence
Computer Networks and Communications
Computer Science Applications
Hardware and Architecture
Information Systems
Electrical and Electronic Engineering

Access to Document

10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134115

Cite this

Kuban, J., & Adegbija, T. (2023). Designing Constant-Timed Accelerators using High-Level Synthesis: A Case Study of ECG Biometric Authentication. In 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134115

Designing Constant-Timed Accelerators using High-Level Synthesis: A Case Study of ECG Biometric Authentication. / Kuban, James; Adegbija, Tosiron.
2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kuban, J & Adegbija, T 2023, Designing Constant-Timed Accelerators using High-Level Synthesis: A Case Study of ECG Biometric Authentication. in 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings, Institute of Electrical and Electronics Engineers Inc., 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023, Hsinchu, Taiwan, Province of China, 4/17/23. https://doi.org/10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134115

Kuban J, Adegbija T. Designing Constant-Timed Accelerators using High-Level Synthesis: A Case Study of ECG Biometric Authentication. In 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc. 2023. (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings). doi: 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134115

Kuban, James ; Adegbija, Tosiron. / Designing Constant-Timed Accelerators using High-Level Synthesis : A Case Study of ECG Biometric Authentication. 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2023. (2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings).

@inproceedings{9a98fdb697484a8fbf24535086533d59,

title = "Designing Constant-Timed Accelerators using High-Level Synthesis: A Case Study of ECG Biometric Authentication",

abstract = "High-level synthesis (HLS) is an increasingly popular approach for rapidly designing complex, high-performance, and energy-efficient application-specific accelerators, enabling a shorter time to market and increased productivity. This paper explores a workflow for generating constant-timed accelerators using generic HLS tools in order to eliminate the timing-based side-channel vulnerabilities intrinsic to accelerators generated using state-of-the-art HLS. Since security, performance, and energy are often conflicting design objectives, we also explore ways to mitigate the design overhead. We demonstrate the workflow using a case study of an ECG biometric authentication system, which exemplifies a real-world system with significant timing side-channel vulnerabilities. Results show that the workflow successfully generates constant-timed accelerators and enables designers to use generic HLS tools, thereby minimizing any negative impacts on the design process.",

author = "James Kuban and Tosiron Adegbija",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 ; Conference date: 17-04-2023 Through 20-04-2023",

year = "2023",

doi = "10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134115",

language = "English (US)",

series = "2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings",

}

TY - GEN

T1 - Designing Constant-Timed Accelerators using High-Level Synthesis

T2 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023

AU - Kuban, James

AU - Adegbija, Tosiron

PY - 2023

Y1 - 2023

N2 - High-level synthesis (HLS) is an increasingly popular approach for rapidly designing complex, high-performance, and energy-efficient application-specific accelerators, enabling a shorter time to market and increased productivity. This paper explores a workflow for generating constant-timed accelerators using generic HLS tools in order to eliminate the timing-based side-channel vulnerabilities intrinsic to accelerators generated using state-of-the-art HLS. Since security, performance, and energy are often conflicting design objectives, we also explore ways to mitigate the design overhead. We demonstrate the workflow using a case study of an ECG biometric authentication system, which exemplifies a real-world system with significant timing side-channel vulnerabilities. Results show that the workflow successfully generates constant-timed accelerators and enables designers to use generic HLS tools, thereby minimizing any negative impacts on the design process.

AB - High-level synthesis (HLS) is an increasingly popular approach for rapidly designing complex, high-performance, and energy-efficient application-specific accelerators, enabling a shorter time to market and increased productivity. This paper explores a workflow for generating constant-timed accelerators using generic HLS tools in order to eliminate the timing-based side-channel vulnerabilities intrinsic to accelerators generated using state-of-the-art HLS. Since security, performance, and energy are often conflicting design objectives, we also explore ways to mitigate the design overhead. We demonstrate the workflow using a case study of an ECG biometric authentication system, which exemplifies a real-world system with significant timing side-channel vulnerabilities. Results show that the workflow successfully generates constant-timed accelerators and enables designers to use generic HLS tools, thereby minimizing any negative impacts on the design process.

UR - http://www.scopus.com/inward/record.url?scp=85162949046&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85162949046&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134115

DO - 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10134115

M3 - Conference contribution

AN - SCOPUS:85162949046

T3 - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

BT - 2023 International VLSI Symposium on Technology, Systems and Applications, VLSI-TSA/VLSI-DAT 2023 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 17 April 2023 through 20 April 2023

ER -

Designing Constant-Timed Accelerators using High-Level Synthesis: A Case Study of ECG Biometric Authentication

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