Design techniques for fault-tolerant systolic arrays

M. O. Esonu, A. J. Al-Khalili, S. Hariri, D. Al-Khalili

Research output: Contribution to journalArticlepeer-review


A systematic approach of designing fault-tolerant systolic architectures is proposed in this paper. In this approach, redundant computations are introduced at the algorithmic level by deriving three versions of a given algorithm. Fault-tolerant systolic array is constructed by merging the corresponding systolic array of the three versions of the algorithm. The merging method attempts to obtain the fault-tolerant systolic array at minimal cost in terms of area and speed. It is based on rescheduling input data, rearranging data flow, and increasing the utilization of the array cells. The resulting design can detect and tolerate all single permanent and temporary faults and the majority of the multiple fault patterns with high probability.

Original languageEnglish (US)
Pages (from-to)151-168
Number of pages18
JournalJournal of VLSI Signal Processing
Issue number1-2
StatePublished - Oct 1995

ASJC Scopus subject areas

  • Signal Processing
  • Information Systems
  • Electrical and Electronic Engineering


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