Abstract
This paper presents the design of a framework for the optimization of a low-power, low-noise, broadband transimpedance amplifier to be used in a fiber optic transceiver. The design is implemented using a 180 nm six-metal-layer digital CMOS process with a 1.8V supply. The performances achieved are a gain of (Formula presented.), a bandwidth of 2.21 GHz, an input referred current noise of (Formula presented.)pA/Hz1/2, and a power dissipation of 13.5 mW.
Original language | English (US) |
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Pages (from-to) | 2785-2800 |
Number of pages | 16 |
Journal | Circuits, Systems, and Signal Processing |
Volume | 34 |
Issue number | 9 |
DOIs | |
State | Published - Sep 30 2015 |
Keywords
- CMOS
- Design optimization
- Fiber optic transceiver
- Nanotechnology
- Transimpedance amplifier
ASJC Scopus subject areas
- Signal Processing
- Applied Mathematics