Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes

Burak Unal, Md Sahil Hassan, Joshua Mack, Nirmal Kumbhare, Ali Akoglu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

We present a modular FPGA-based testbed to accelerate the study of low-density parity-check codes (LDPC). This testbed is composed of controller, codeword generator, noise generator, random number generator, LDPC decoder, and statistical analysis modules. The LDPC decoder module is replaceable to enable development or study of new or existing hard-decision-based decoders. We demonstrate our testbed's ability to reduce the timescale of error correction and error pattern analysis through case studies involving the Gallager B (GaB) and Probabilistic Gallager B (PGaB) algorithms. We contextualize the throughput and execution time performance of our framework, running on a Xilinx Zynq XC7Z020 FPGA, with reference CPU (Intel Xeon) and GPGPU (Tesla K40) implementations of the PGaB algorithm. While the single threaded CPU-based testbed and the reference GPU testbed achieve throughputs of 219 Kb/s and 3608 Kb/s respectively, the FPGA-based testbed achieves 9172 Mb/s. This corresponds to reducing the time scale of error correction analysis on PGaB, at previously untested error resolutions, to less than a day from an estimated 199 years on a single general purpose processor and 12 years on the GPU. We finally demonstrate the utility of our testbed by completing the first simulation on identifying all possible codewords with four errors that are not correctable by GaB. We reduce the time scale of this simulation, which requires processing 117 billion codewords, to 4.5 hours from an estimated 488 days on the GPU and 7803 days on CPU. Our open-source, modular and parameterized testbed allows researchers rapidly evaluate error correction performance of the target decoder algorithm and collect statistical data essential to exploring algorithmic improvement opportunities.

Original languageEnglish (US)
Title of host publication2019 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2019
EditorsDavid Andrews, Rene Cumplido, Claudia Feregrino, Marco Platzner
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728119571
DOIs
StatePublished - Dec 2019
Externally publishedYes
Event2019 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2019 - Cancun, Mexico
Duration: Dec 9 2019Dec 11 2019

Publication series

Name2019 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2019

Conference

Conference2019 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2019
Country/TerritoryMexico
CityCancun
Period12/9/1912/11/19

Keywords

  • Error-correcting codes
  • FPGA testbed
  • GPU
  • Low density parity check (LDPC) codes

ASJC Scopus subject areas

  • Computer Science Applications
  • Software

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