Design of High Throughput FPGA-Based Testbed for Accelerating Error Characterization of LDPC Codes

We present a modular FPGA-based testbed to accelerate the study of low-density parity-check codes (LDPC). This testbed is composed of controller, codeword generator, noise generator, random number generator, LDPC decoder, and statistical analysis modules. The LDPC decoder module is replaceable to enable development or study of new or existing hard-decision-based decoders. We demonstrate our testbed's ability to reduce the timescale of error correction and error pattern analysis through case studies involving the Gallager B (GaB) and Probabilistic Gallager B (PGaB) algorithms. We contextualize the throughput and execution time performance of our framework, running on a Xilinx Zynq XC7Z020 FPGA, with reference CPU (Intel Xeon) and GPGPU (Tesla K40) implementations of the PGaB algorithm. While the single threaded CPU-based testbed and the reference GPU testbed achieve throughputs of 219 Kb/s and 3608 Kb/s respectively, the FPGA-based testbed achieves 9172 Mb/s. This corresponds to reducing the time scale of error correction analysis on PGaB, at previously untested error resolutions, to less than a day from an estimated 199 years on a single general purpose processor and 12 years on the GPU. We finally demonstrate the utility of our testbed by completing the first simulation on identifying all possible codewords with four errors that are not correctable by GaB. We reduce the time scale of this simulation, which requires processing 117 billion codewords, to 4.5 hours from an estimated 488 days on the GPU and 7803 days on CPU. Our open-source, modular and parameterized testbed allows researchers rapidly evaluate error correction performance of the target decoder algorithm and collect statistical data essential to exploring algorithmic improvement opportunities.