TY - GEN
T1 - Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs)
AU - Kodi, Avinash
AU - Louri, Ahmed
AU - Wang, Janet
PY - 2009
Y1 - 2009
N2 - Network-on-chip (NoC) architectures are fast becoming an attractive solution to address the interconnect delay problems in chip multiprocessors (CMPs). However, increased power dissipation and limited performance improvements have hindered the wide-deployment of NoCs. In this paper, we combine two techniques of adaptive channel buffers and router pipeline bypassing to simultaneously reduce power consumption and improve performance. Power consumption can be decreased by reducing the size of the router buffers. However, as reducing router buffers alone will significantly degrade performance, we compensate by utilizing the newly proposed dual-function channel buffers that allow flits to be stored on wires when required. Network bypassing technique, on the other hand, allows flits to bypass the router pipeline and thereby avoid the router buffers altogether. We combine the two techniques and attempt to keep the flits on the wires from source to destination. Our simulation results of the proposed methodology combining the two techniques, yield a overall power reduction of 62% over the baseline and improve performance (throughput and latency) by more than 10%.
AB - Network-on-chip (NoC) architectures are fast becoming an attractive solution to address the interconnect delay problems in chip multiprocessors (CMPs). However, increased power dissipation and limited performance improvements have hindered the wide-deployment of NoCs. In this paper, we combine two techniques of adaptive channel buffers and router pipeline bypassing to simultaneously reduce power consumption and improve performance. Power consumption can be decreased by reducing the size of the router buffers. However, as reducing router buffers alone will significantly degrade performance, we compensate by utilizing the newly proposed dual-function channel buffers that allow flits to be stored on wires when required. Network bypassing technique, on the other hand, allows flits to bypass the router pipeline and thereby avoid the router buffers altogether. We combine the two techniques and attempt to keep the flits on the wires from source to destination. Our simulation results of the proposed methodology combining the two techniques, yield a overall power reduction of 62% over the baseline and improve performance (throughput and latency) by more than 10%.
KW - Channel Buffers
KW - Network-on-Chips (NoCs)
KW - Router Bypassing
UR - http://www.scopus.com/inward/record.url?scp=67649642145&partnerID=8YFLogxK
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U2 - 10.1109/ISQED.2009.4810399
DO - 10.1109/ISQED.2009.4810399
M3 - Conference contribution
AN - SCOPUS:67649642145
SN - 9781424429530
T3 - Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
SP - 826
EP - 832
BT - Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
T2 - 10th International Symposium on Quality Electronic Design, ISQED 2009
Y2 - 16 March 2009 through 18 March 2009
ER -