Design of a scalable RF microarchitecture for heterogeneous MPSoCs

With the rapid emergence of multiprocessor system-on-chip (MPSoC) designs, the on-chip communication fabric becomes the performance determinant. With the high data-rate, low power and ultra-short range interconnection provided by UWB technology, a new on-chip communication system, dubbed wireless network-on-chip (Wi-NoC), has been proposed for nanoscale MPSoCs. In this work, we will develop the RF microarchitecture of WiNoC where the RF nodes are designed to fulfill the functions of distributed table routing, multi-channel arbitration, virtual output queuing, and distributed flow control. A flexible RF infrastructure will be established where RF nodes are properly distributed and IP cores are clustered. Consequently, a performance-cost effective topology will be formed. Our simulation studies based on synthetic traffics demonstrate the network efficiency and scalability of WiNoC.