Design and implementation of a MicroBlaze-based warp processor

Roman Lysecky, Frank Vahid

Research output: Contribution to journalArticlepeer-review

43 Scopus citations


While soft processor cores provided by FPGA vendors offer designers with increased flexibility, such processors typically incur penalties in performance and energy consumption compared to hard processor core alternatives. The recently developed technology of warp processing can help reduce those penalties. Warp processing is the dynamic and transparent transformation of critical software regions from microprocessor execution to much faster circuit execution on an FPGA. In this article, we describe an implementation of a warp processor on a Xilinx Virtex-II Pro and Spartan3 FPGAs incorporating one or more MicroBlaze soft processor cores. We further provide a detailed analysis of the energy overhead of dynamically partitioning an application's kernels to hardware executing within an FPGA. Considering an implementation that periodically partitions the executing application once every minute, a MicroBlaze-based warp processor implemented on a Spartan3 FPGA achieves average speedups of 5.8× and energy reductions of 49% compared to the MicroBlaze soft processor core aloneproviding competitive performance and energy consumption compared to existing hard processor cores.

Original languageEnglish (US)
Article number22
JournalTransactions on Embedded Computing Systems
Issue number3
StatePublished - Apr 1 2009


  • Configurable logic
  • Dynamic optimization
  • FPGA
  • Hardware/software partitioning
  • Just-in-time (JIT) compilation
  • Soft processor cores
  • Warp processors

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture


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