Delay uncertainty reduction by gate splitting

Vineet Agarwal; Jin Sun; Janet M. Wang

doi:10.1109/TCSII.2009.2015394

Delay uncertainty reduction by gate splitting

Vineet Agarwal, Jin Sun, Janet M. Wang

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

Traditional timing-variation reduction techniques are only able to decrease gate delay variation by incurring a delay overhead. In this brief, we propose a novel and effective splitting-based variation reduction technique for gates. We developed a new tool called Timing Uncertainty Reduction by Gate Splitting (TURGS), which reduces the timing variations of a circuit and presents little delay overhead at the primary output. Our experimental results show that TURGS achieves up to 20% improvement in timing variation for gates.

Original language	English (US)
Pages (from-to)	295-299
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	56
Issue number	4
DOIs	https://doi.org/10.1109/TCSII.2009.2015394
State	Published - 2009

Keywords

Delay uncertainty reduction
Gate cloning
Gate split
Process variation

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/TCSII.2009.2015394

Cite this

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title = "Delay uncertainty reduction by gate splitting",

abstract = "Traditional timing-variation reduction techniques are only able to decrease gate delay variation by incurring a delay overhead. In this brief, we propose a novel and effective splitting-based variation reduction technique for gates. We developed a new tool called Timing Uncertainty Reduction by Gate Splitting (TURGS), which reduces the timing variations of a circuit and presents little delay overhead at the primary output. Our experimental results show that TURGS achieves up to 20% improvement in timing variation for gates.",

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AU - Sun, Jin

AU - Wang, Janet M.

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AB - Traditional timing-variation reduction techniques are only able to decrease gate delay variation by incurring a delay overhead. In this brief, we propose a novel and effective splitting-based variation reduction technique for gates. We developed a new tool called Timing Uncertainty Reduction by Gate Splitting (TURGS), which reduces the timing variations of a circuit and presents little delay overhead at the primary output. Our experimental results show that TURGS achieves up to 20% improvement in timing variation for gates.

KW - Delay uncertainty reduction

KW - Gate cloning

KW - Gate split

KW - Process variation

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ER -

Delay uncertainty reduction by gate splitting

Abstract

Keywords

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