TY - GEN
T1 - Construction of memory circuits using unreliable components based on low-density parity-check codes
AU - Ivković, Miloš
AU - Chilappagari, Shashi Kiran
AU - Vasić, Bane
PY - 2006
Y1 - 2006
N2 - In this paper, we analyze storage circuits constructed from unreliable memory components. We propose a memory construction, using low-density parity-check codes, based on a construction originally made by Taylor. The storage circuit consists of unreliable memory cells along with a correcting circuit. The correcting circuit is also constructed from unreliable logic gates along with a small number of perfect gates. The modified construction enables the memory device to perform better than the original construction. We present numerical results supporting our claims.
AB - In this paper, we analyze storage circuits constructed from unreliable memory components. We propose a memory construction, using low-density parity-check codes, based on a construction originally made by Taylor. The storage circuit consists of unreliable memory cells along with a correcting circuit. The correcting circuit is also constructed from unreliable logic gates along with a small number of perfect gates. The modified construction enables the memory device to perform better than the original construction. We present numerical results supporting our claims.
UR - http://www.scopus.com/inward/record.url?scp=50949131392&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=50949131392&partnerID=8YFLogxK
U2 - 10.1109/GLOCOM.2006.159
DO - 10.1109/GLOCOM.2006.159
M3 - Conference contribution
AN - SCOPUS:50949131392
SN - 142440357X
SN - 9781424403578
T3 - GLOBECOM - IEEE Global Telecommunications Conference
BT - IEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference
T2 - IEEE GLOBECOM 2006 - 2006 Global Telecommunications Conference
Y2 - 27 November 2006 through 1 December 2006
ER -