Conjoining soft-core FPGA processors

David Sheldon; Rakesh Kumar; Frank Vahid; Dean Tullsen; Roman Lysecky

doi:10.1109/ICCAD.2006.320015

Conjoining soft-core FPGA processors

David Sheldon, Rakesh Kumar, Frank Vahid, Dean Tullsen, Roman Lysecky

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

13 Scopus citations

Abstract

Soft-core programmable processors on field-programmable gate arrays (FPGAs) can be custom synthesized to instantiate only those hardware units, such as multipliers and floating-point units, that an application requires to meet performance demands, thus minimizing soft-core size on the FPGA. Conjoining processors, meaning to share hardware units among two or more processors, can further reduce soft-core size, leaving more resources for other circuits such as custom coprocessors. Using Xilinx MicroBlaze coprocessors and standard embedded system benchmarks, we show that conjoining two processors can provide 16% processor size reductions on average, with less than 1% cycle count overhead. We introduce an efficient dynamic-programming-based exploration method to find the best custom instantiation of hardware units, considering both standalone and conjoined options, for soft-core processors.

Original language	English (US)
Title of host publication	Proceedings of the 2006 International Conference on Computer-Aided Design, ICCAD
Pages	694-701
Number of pages	8
DOIs	https://doi.org/10.1109/ICCAD.2006.320015
State	Published - 2006
Event	2006 International Conference on Computer-Aided Design, ICCAD - San Jose, CA, United States Duration: Nov 5 2006 → Nov 9 2006

Publication series

Name	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
ISSN (Print)	1092-3152

Other

Other	2006 International Conference on Computer-Aided Design, ICCAD
Country/Territory	United States
City	San Jose, CA
Period	11/5/06 → 11/9/06

Keywords

Conjoined processors
Customization
FPGAs
Parameterized platforms
Soft-core processors
Tuning

ASJC Scopus subject areas

Software
Computer Science Applications
Computer Graphics and Computer-Aided Design

Access to Document

10.1109/ICCAD.2006.320015

Cite this

Conjoining soft-core FPGA processors. / Sheldon, David; Kumar, Rakesh; Vahid, Frank et al.
Proceedings of the 2006 International Conference on Computer-Aided Design, ICCAD. 2006. p. 694-701 4110254 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sheldon, D, Kumar, R, Vahid, F, Tullsen, D & Lysecky, R 2006, Conjoining soft-core FPGA processors. in Proceedings of the 2006 International Conference on Computer-Aided Design, ICCAD., 4110254, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, pp. 694-701, 2006 International Conference on Computer-Aided Design, ICCAD, San Jose, CA, United States, 11/5/06. https://doi.org/10.1109/ICCAD.2006.320015

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Conjoining soft-core FPGA processors

Abstract

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Keywords

ASJC Scopus subject areas

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