Abstract
A simulation environment for prediction of electrical characteristics of integrated circuit packaging structures is described. The simulation shell, Packaging Design Support Environment (PDSE), integrates tools for modeling and simulation of electrical characteristics in VLSI packages. It also provides facilities for supporting design of VLSI packages. Two simulation tools model inductance and capacitance for multiconductor, multidielectric, two-dimensional structures with lossy dielectrics. Another accepts the L and C matrices and computes pulse response characteristics of uniform multiple, coupled, lossless transmission lines which are terminated at discrete points with R, L, and C elements. The design process in PDSE proceeds in three major phases: modeling, simulation, and evaluation. These processes are interactive and allow the designer to refine a design model, modify simulation experiments, and apply various evaluation processes.
| Original language | English (US) |
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| Pages | 237-241 |
| Number of pages | 5 |
| State | Published - 1989 |
| Event | Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA Duration: Oct 2 1989 → Oct 4 1989 |
Other
| Other | Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors |
|---|---|
| City | Cambridge, MA, USA |
| Period | 10/2/89 → 10/4/89 |
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering