Compilation Framework for Dynamically Reconfigurable Array Architectures

This paper presents a compilation and scheduling framework for high-performance mapping of computationally-intensive kernels on Dynamically Reconfigurable Array Architectures. We showcase the framework for Domain Adaptive Processor (DAP) - an array accelerator designed for signal processing and communication workloads that has near-ASIC energy efficiency. DAP consists of an array of homogeneous Processing Element (PE) clusters, where each PE cluster consists of heterogeneous PEs capable of executing Very-Long-Instruction-Word (VLIW) instructions. We introduce a virtual Instruction Set Architecture (ISA) and a sequential assembly to low-level micro-code conversion mechanism. The proposed work includes optimization techniques that transform the low-level micro-code into compact VLIW instructions resulting in an average instruction count reduction by 1.8x and a significant increase in PE utilization. In addition, we demonstrate rate-aware software-based pipelining of the VLIW code resulting in an improvement in throughput by up to 15x for linear algebra and signal processing kernels. Further, we propose a scheduler that is capable of automatically resolving data dependencies between the threads at the micro-instruction level and accurately schedule custom dataflows overcoming the limitations of fixed mapping and scheduling schemes used in traditional CGRA compilers. These contributions together, provide a compilation flow for dynamically reconfigurable array architectures leading to an improvement in ease of programmability and productivity while ensuring low-level implementation flexibility for performance-critical applications.