TY - JOUR
T1 - Collective Bit Flipping-Based Decoding of Quantum LDPC Codes
AU - Chytas, Dimitris
AU - Raveendran, Nithin
AU - Vasic, Bane
N1 - Publisher Copyright:
© 1972-2012 IEEE.
PY - 2025
Y1 - 2025
N2 - Quantum low-density parity-check (QLDPC) codes have been proven to achieve higher minimum distances at higher code rates than surface codes. However, this family of codes must cope with the stringent latency constraints imposed by quantum technology and tends to exhibit poor performance under iterative decoding, especially when the variable degree is low. In this work, we improve both the error correction performance and decoding latency of variable degree-3 (dv-3) QLDPC codes under iterative decoding. Firstly, we perform a detailed analysis of the structure of a well-known family of QLDPC codes, i.e., hypergraph product-based codes. Then, we propose a decoding approach that stems from the knowledge of harmful configurations apparent in these codes. Our decoding scheme is based on applying a modified version of bit flipping (BF) decoding, namely two-bit bit flipping (TBF) decoding, which adds more degrees of freedom to BF decoding. The granularity offered by TBF decoding helps us design sets of decoders that operate in parallel and can collectively decode error patterns appearing in harmful configurations of the code, thus addressing both the latency and performance requirements. Finally, simulation results demonstrate that the proposed decoding scheme surpasses other iterative decoding approaches for various dv-3 QLDPC codes.
AB - Quantum low-density parity-check (QLDPC) codes have been proven to achieve higher minimum distances at higher code rates than surface codes. However, this family of codes must cope with the stringent latency constraints imposed by quantum technology and tends to exhibit poor performance under iterative decoding, especially when the variable degree is low. In this work, we improve both the error correction performance and decoding latency of variable degree-3 (dv-3) QLDPC codes under iterative decoding. Firstly, we perform a detailed analysis of the structure of a well-known family of QLDPC codes, i.e., hypergraph product-based codes. Then, we propose a decoding approach that stems from the knowledge of harmful configurations apparent in these codes. Our decoding scheme is based on applying a modified version of bit flipping (BF) decoding, namely two-bit bit flipping (TBF) decoding, which adds more degrees of freedom to BF decoding. The granularity offered by TBF decoding helps us design sets of decoders that operate in parallel and can collectively decode error patterns appearing in harmful configurations of the code, thus addressing both the latency and performance requirements. Finally, simulation results demonstrate that the proposed decoding scheme surpasses other iterative decoding approaches for various dv-3 QLDPC codes.
KW - bit flipping decoding
KW - error-floor
KW - hypergraph-product codes
KW - QLDPC codes
KW - symmetric stabilizers
KW - trapping sets
UR - http://www.scopus.com/inward/record.url?scp=85216882990&partnerID=8YFLogxK
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U2 - 10.1109/TCOMM.2025.3535897
DO - 10.1109/TCOMM.2025.3535897
M3 - Article
AN - SCOPUS:85216882990
SN - 0090-6778
JO - IEEE Transactions on Communications
JF - IEEE Transactions on Communications
ER -