Circuits as Graphs: A Review of Graph Learning for Secure and Trustworthy Hardware

Modern Integrated Circuits (ICs) are highly interconnected, making graph representation a natural foundation for hardware security analysis. In recent years, graph-based approaches have gained significant traction in addressing a wide range of hardware security challenges, starting from classical subgraph matching to advanced Graph Neural Network (GNN) models. This paper presents a comprehensive review of graph-centric methods across key domains, including hardware trojan detection and localization, intellectual property piracy and watermark protection, side-channel leakage assessment, and hardware vulnerability analysis. We first discuss how hardware designs can be modeled using different graph modalities and how these representations enable machine learning models to capture structural and functional properties. We then organize existing studies into a unified taxonomy linking problem type, graph formulation, and learning approach. Furthermore, we highlight hardware design to graph conversion tools, datasets, performance trends, and open issues in scalability, explainability, and resilience to adversarial manipulation. Finally, the paper outlines promising research directions such as multi-view graph representations, cross-level GNN integration, effective trojan-node localization, and trustworthy graph learning for secure-by-design hardware. Overall, this review positions graph-based learning as a central enabler for the next generation of hardware security methodologies.