Building extensible routers using network processors

Nadia Shalaby; Andy Bavier; Yitzchak Gottlieb; Scott Karlin; Larry Peterson; Xiaohu Qie; Tammo Spalink; Mike Wawrzoniak

doi:10.1002/spe.667

Building extensible routers using network processors

Nadia Shalaby, Andy Bavier, Yitzchak Gottlieb, Scott Karlin, Larry Peterson, Xiaohu Qie, Tammo Spalink, Mike Wawrzoniak

Research output: Contribution to journal › Article › peer-review

Abstract

This paper describes our effort to build extensible routers using a combination of general-purpose and network processors. We emphasize five overriding challenges that dictate our design decisions: (1) optimal resource allocation; (2) efficient but flexible scheduling of the CPU; (3) maintaining overall router robustness; (4) maximizing router performance; and (5) providing sufficient extensibility to enable the injection of new functionality into the router. We adopt a hierarchical architecture, in which packet flows traverse a range of processing/forwarding paths, thereby partitioning hardware and software in concert. This paper both presents the architecture, and describes our experiences implementing the architecture and addressing the five design challenges in a prototype built from Intel IXP 1200 and a Pentium.

Original language	English (US)
Pages (from-to)	1155-1194
Number of pages	40
Journal	Software - Practice and Experience
Volume	35
Issue number	12
DOIs	https://doi.org/10.1002/spe.667
State	Published - Oct 2005
Externally published	Yes

Keywords

CPU scheduling
Extensible router design
Hierarchical router architecture
Intel IXP 1200
Network processors
Resource allocation

ASJC Scopus subject areas

Software

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10.1002/spe.667

Cite this

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AU - Shalaby, Nadia

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AU - Gottlieb, Yitzchak

AU - Karlin, Scott

AU - Peterson, Larry

AU - Qie, Xiaohu

AU - Spalink, Tammo

AU - Wawrzoniak, Mike

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Building extensible routers using network processors

Abstract

Keywords

ASJC Scopus subject areas

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