Abstract
In a circuit, timing errors occur when a logic gate output does not switch before the clock rising edge. In this letter, we consider Gallager B decoders under timing errors, following the error model derived by Amaricai et al. from SPICE measurements. For this model, we provide a theoretical analysis of the performance of LDPC decoders. This letter is based on the analysis of the computation trees of the decoder free of logic gate errors and of the decoder with timing errors. As a main result, we show that as the number of iterations goes to infinity, the error probability of the decoder with timing errors converges to the error probability of the logic gate error-free decoder. Monte Carlo simulations confirm this result even for moderate code lengths, which is in accordance with the experimental observations.
Original language | English (US) |
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Article number | 7805222 |
Pages (from-to) | 698-701 |
Number of pages | 4 |
Journal | IEEE Communications Letters |
Volume | 21 |
Issue number | 4 |
DOIs | |
State | Published - Apr 2017 |
Keywords
- Low-density parity check codes
- computation trees
- faulty Gallager B decoders
- timing errors
ASJC Scopus subject areas
- Modeling and Simulation
- Computer Science Applications
- Electrical and Electronic Engineering