TY - GEN
T1 - ArC
T2 - 2019 International Symposium on Memory Systems, MEMSYS 2019
AU - Gajaria, Dhruv
AU - Adegbija, Tosiron
N1 - Publisher Copyright:
© 2019 Copyright held by the owner/author(s). Publication rights licensed to Association for Computing Machinery.
PY - 2019/9/30
Y1 - 2019/9/30
N2 - Relaxed retention (or volatile) spin-transfer torque RAM (STT-RAM) has been widely studied as a way to reduce STT-RAM’s write energy and latency overheads. Given a relaxed retention time STT-RAM level one (L1) cache, we analyze the impacts of dynamic voltage and frequency scaling (DVFS)—a common optimization in modern processors—on STT-RAM L1 cache design. Our analysis reveals that, apart from the fact that different applications may require different retention times, the clock frequency, which is typically ignored in most STT-RAM studies, may also significantly impact applications’ retention time needs. Based on our findings, we propose an asymmetric-retention core (ARC) design for multicore architectures. ARC features retention time heterogeneity to specialize STT-RAM retention times to applications’ needs. We also propose a runtime prediction model to determine the best core on which to run an application, based on the applications’ characteristics, their retention time requirements, and available DVFS settings. Results reveal that the proposed approach can reduce the average cache energy by 20.19% and overall processor energy by 7.66%, compared to a homogeneous STT-RAM cache design.
AB - Relaxed retention (or volatile) spin-transfer torque RAM (STT-RAM) has been widely studied as a way to reduce STT-RAM’s write energy and latency overheads. Given a relaxed retention time STT-RAM level one (L1) cache, we analyze the impacts of dynamic voltage and frequency scaling (DVFS)—a common optimization in modern processors—on STT-RAM L1 cache design. Our analysis reveals that, apart from the fact that different applications may require different retention times, the clock frequency, which is typically ignored in most STT-RAM studies, may also significantly impact applications’ retention time needs. Based on our findings, we propose an asymmetric-retention core (ARC) design for multicore architectures. ARC features retention time heterogeneity to specialize STT-RAM retention times to applications’ needs. We also propose a runtime prediction model to determine the best core on which to run an application, based on the applications’ characteristics, their retention time requirements, and available DVFS settings. Results reveal that the proposed approach can reduce the average cache energy by 20.19% and overall processor energy by 7.66%, compared to a homogeneous STT-RAM cache design.
KW - Cache
KW - DVFS
KW - Energy efficient systems
KW - Nonvolatile memory
KW - Retention time
KW - Spin-Transfer Torque RAM (STTRAM)
KW - Write energy
KW - Write latency
UR - https://www.scopus.com/pages/publications/85075864800
UR - https://www.scopus.com/pages/publications/85075864800#tab=citedBy
U2 - 10.1145/3357526.3357553
DO - 10.1145/3357526.3357553
M3 - Conference contribution
AN - SCOPUS:85075864800
T3 - ACM International Conference Proceeding Series
SP - 439
EP - 450
BT - MEMSYS 2019 - Proceedings of the International Symposium on Memory Systems
PB - Association for Computing Machinery
Y2 - 30 September 2019 through 3 October 2019
ER -