Analytical performance of one-step majority logic decoding of regular LDPC codes

Rathnakumar Radhakrishnan; Sundararajan Sankaranarayanan; Bane Vasić

doi:10.1109/ISIT.2007.4557231

Analytical performance of one-step majority logic decoding of regular LDPC codes

Rathnakumar Radhakrishnan, Sundararajan Sankaranarayanan, Bane Vasić

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

In this paper, we present a combinatorial algorithm to calculate the exact bit error rate performance of regular low-density parity check codes under one-step majority logic decoding. Majority logic decoders have regained importance in nano-scale memories due to their resilience to both memory and logic gate failures. This result is an extension of the work of Rudolph on error correction capability of majority-logic decoders.

Original language	English (US)
Title of host publication	Proceedings - 2007 IEEE International Symposium on Information Theory, ISIT 2007
Pages	231-235
Number of pages	5
DOIs	https://doi.org/10.1109/ISIT.2007.4557231
State	Published - 2007
Event	2007 IEEE International Symposium on Information Theory, ISIT 2007 - Nice, France Duration: Jun 24 2007 → Jun 29 2007

Publication series

Name	IEEE International Symposium on Information Theory - Proceedings
ISSN (Print)	2157-8101

Other

Other	2007 IEEE International Symposium on Information Theory, ISIT 2007
Country/Territory	France
City	Nice
Period	6/24/07 → 6/29/07

ASJC Scopus subject areas

Theoretical Computer Science
Information Systems
Modeling and Simulation
Applied Mathematics

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10.1109/ISIT.2007.4557231

Cite this

Analytical performance of one-step majority logic decoding of regular LDPC codes. / Radhakrishnan, Rathnakumar; Sankaranarayanan, Sundararajan; Vasić, Bane.
Proceedings - 2007 IEEE International Symposium on Information Theory, ISIT 2007. 2007. p. 231-235 4557231 (IEEE International Symposium on Information Theory - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Radhakrishnan, R, Sankaranarayanan, S & Vasić, B 2007, Analytical performance of one-step majority logic decoding of regular LDPC codes. in Proceedings - 2007 IEEE International Symposium on Information Theory, ISIT 2007., 4557231, IEEE International Symposium on Information Theory - Proceedings, pp. 231-235, 2007 IEEE International Symposium on Information Theory, ISIT 2007, Nice, France, 6/24/07. https://doi.org/10.1109/ISIT.2007.4557231

@inproceedings{e03b45a0eca340eeb1f0e08a566e6d67,

title = "Analytical performance of one-step majority logic decoding of regular LDPC codes",

abstract = "In this paper, we present a combinatorial algorithm to calculate the exact bit error rate performance of regular low-density parity check codes under one-step majority logic decoding. Majority logic decoders have regained importance in nano-scale memories due to their resilience to both memory and logic gate failures. This result is an extension of the work of Rudolph on error correction capability of majority-logic decoders.",

author = "Rathnakumar Radhakrishnan and Sundararajan Sankaranarayanan and Bane Vasi{\'c}",

year = "2007",

doi = "10.1109/ISIT.2007.4557231",

language = "English (US)",

isbn = "1424414296",

series = "IEEE International Symposium on Information Theory - Proceedings",

pages = "231--235",

booktitle = "Proceedings - 2007 IEEE International Symposium on Information Theory, ISIT 2007",

note = "2007 IEEE International Symposium on Information Theory, ISIT 2007 ; Conference date: 24-06-2007 Through 29-06-2007",

}

TY - GEN

T1 - Analytical performance of one-step majority logic decoding of regular LDPC codes

AU - Radhakrishnan, Rathnakumar

AU - Sankaranarayanan, Sundararajan

AU - Vasić, Bane

PY - 2007

Y1 - 2007

N2 - In this paper, we present a combinatorial algorithm to calculate the exact bit error rate performance of regular low-density parity check codes under one-step majority logic decoding. Majority logic decoders have regained importance in nano-scale memories due to their resilience to both memory and logic gate failures. This result is an extension of the work of Rudolph on error correction capability of majority-logic decoders.

AB - In this paper, we present a combinatorial algorithm to calculate the exact bit error rate performance of regular low-density parity check codes under one-step majority logic decoding. Majority logic decoders have regained importance in nano-scale memories due to their resilience to both memory and logic gate failures. This result is an extension of the work of Rudolph on error correction capability of majority-logic decoders.

UR - http://www.scopus.com/inward/record.url?scp=51649116409&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=51649116409&partnerID=8YFLogxK

U2 - 10.1109/ISIT.2007.4557231

DO - 10.1109/ISIT.2007.4557231

M3 - Conference contribution

AN - SCOPUS:51649116409

SN - 1424414296

SN - 9781424414291

T3 - IEEE International Symposium on Information Theory - Proceedings

SP - 231

EP - 235

BT - Proceedings - 2007 IEEE International Symposium on Information Theory, ISIT 2007

T2 - 2007 IEEE International Symposium on Information Theory, ISIT 2007

Y2 - 24 June 2007 through 29 June 2007

ER -

Analytical performance of one-step majority logic decoding of regular LDPC codes

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