Analysis of techniques to improve protocol processing latency

D. Mosberger, L. L. Peterson, P. C. Bridges, S. O'Malley

Research output: Contribution to journalConference articlepeer-review

20 Scopus citations


This paper describes several techniques designed to improve protocol latency, and reports on their effectiveness when measured on a modern RISC machine employing the DEC Alpha processor. We found that the memory system - which has long been known to dominate network throughput - is also a key factor on protocol latency. As a result, improving instruction cache effectiveness can greatly reduce protocol processing overheads. An important metric in this context is the memory cycles per instructions (mCPI), which is the average number of cycles that an instruction stalls waiting for a memory access to complete. The techniques presented in this paper reduce the mCPI by a factor of 1.35 to 5.8. In analyzing the effectiveness of the techniques, we also present a detailed study of the protocol processing behavior of two protocol stacks - TCP/IP and RPC - on a modern RISC processor.

Original languageEnglish (US)
Pages (from-to)73-84
Number of pages12
JournalComputer Communication Review
Issue number4
StatePublished - 1996
EventProceedings of the 1996 ACM SIGCOMM Conference on Applications, Technologies, Architectures, and Protocols for Computer Communications - Stanford, CA, USA
Duration: Aug 26 1996Aug 30 1996

ASJC Scopus subject areas

  • Software
  • Computer Networks and Communications


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