TY - GEN
T1 - Analysis of one step majority logic decoders constructed from faulty gates
AU - Chilappagari, Shashi Kiran
AU - Ivković, Miloš
AU - Vasić, Bane
PY - 2006
Y1 - 2006
N2 - In this paper we propose an analytical method to evaluate the performance of one step majority logic decoders constructed from faulty gates. We analyze the decoder under the assumption that the gates fail independently. We calculate the average bit error probability of such a decoder and apply the method to the special case of projective geometry codes. The method, however, applies to any regular low-density parity-check code of girth at least six but the calculations are much simpler for the projective geometry codes. We present results for the bit error rate performance of four codes from projective planes.
AB - In this paper we propose an analytical method to evaluate the performance of one step majority logic decoders constructed from faulty gates. We analyze the decoder under the assumption that the gates fail independently. We calculate the average bit error probability of such a decoder and apply the method to the special case of projective geometry codes. The method, however, applies to any regular low-density parity-check code of girth at least six but the calculations are much simpler for the projective geometry codes. We present results for the bit error rate performance of four codes from projective planes.
UR - http://www.scopus.com/inward/record.url?scp=39049152953&partnerID=8YFLogxK
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U2 - 10.1109/ISIT.2006.261713
DO - 10.1109/ISIT.2006.261713
M3 - Conference contribution
AN - SCOPUS:39049152953
SN - 1424405041
SN - 9781424405046
T3 - IEEE International Symposium on Information Theory - Proceedings
SP - 469
EP - 473
BT - Proceedings - 2006 IEEE International Symposium on Information Theory, ISIT 2006
T2 - 2006 IEEE International Symposium on Information Theory, ISIT 2006
Y2 - 9 July 2006 through 14 July 2006
ER -