TY - GEN
T1 - Analysis and implementation of resource efficient probabilistic Gallager B LDPC decoder
AU - Unal, Burak
AU - Ghaffari, Fakhreddine
AU - Akoglu, Ali
AU - Declercq, David
AU - Vasic, Bane
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/8/11
Y1 - 2017/8/11
N2 - Low-Density-Parity-Check (LDPC) codes have gained popularity in communication systems and standards due to their capacity-approaching error-correction performance. In this paper, we first expose the tradeoff between decoding performance and hardware performance across three LDPC hard-decision decoding algorithms: Gallager B (GaB), Gradient Descent Bit Flipping (GDBF), and Probabilistic Gradient Descent Bit Flipping (PGDBF). We show that GaB architecture delivers the best throughput while using fewest Field Programmable Gate Array (FPGA) resources, however performs the worst in terms of decoding performance. We then modify the GaB architecture, introduce a new Probabilistic stimulation function (PGaB), and achieve dramatic decoding performance improvement over the GaB, exceeding the performance of GDBF, without sacrificing its superior maximum operating frequency.
AB - Low-Density-Parity-Check (LDPC) codes have gained popularity in communication systems and standards due to their capacity-approaching error-correction performance. In this paper, we first expose the tradeoff between decoding performance and hardware performance across three LDPC hard-decision decoding algorithms: Gallager B (GaB), Gradient Descent Bit Flipping (GDBF), and Probabilistic Gradient Descent Bit Flipping (PGDBF). We show that GaB architecture delivers the best throughput while using fewest Field Programmable Gate Array (FPGA) resources, however performs the worst in terms of decoding performance. We then modify the GaB architecture, introduce a new Probabilistic stimulation function (PGaB), and achieve dramatic decoding performance improvement over the GaB, exceeding the performance of GDBF, without sacrificing its superior maximum operating frequency.
KW - FPGA architectures
KW - High-performance probabibilistic hard-decision LDPC decoders
UR - http://www.scopus.com/inward/record.url?scp=85034423703&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85034423703&partnerID=8YFLogxK
U2 - 10.1109/NEWCAS.2017.8010173
DO - 10.1109/NEWCAS.2017.8010173
M3 - Conference contribution
AN - SCOPUS:85034423703
T3 - Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017
SP - 333
EP - 336
BT - Proceedings - 2017 IEEE 15th International New Circuits and Systems Conference, NEWCAS 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th IEEE International New Circuits and Systems Conference, NEWCAS 2017
Y2 - 25 June 2017 through 28 June 2017
ER -