An analytical model for evaluating static power of homogeneous FPGA architectures

Yoon Kah Leow, Ali Akoglu, Susan Lysecky

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


As capacity of the field-programmable gate arrays (FPGAs) continues to increase, power dissipated in the logic and routing resources has become a critical concern for FPGA architects. Recent studies have shown that static power is fast approaching the dynamic power in submicron devices. In this article, we propose an analytical model for relating homogeneous island-style-based FPGA architecture to static power. Current FPGA power models are tightly coupled with CAD tools. Our CAD-independent model captures the static power for a given FPGA architecture based on estimates of routing and logic resource utilizations from a pre-technology mapped netlist. We observe an average correlation ratio (C-Ratio) of 95% and a minimum absolute percentage error (MAPE) rate of 15% with respect to the experimental results generated by the Versatile Placement Routing (VPR) tool over the MCNC benchmarks. Our model offers application engineers and FPGA architects the capability to evaluate the impact of their design choices on static power without having to go through CAD-intensive investigations.

Original languageEnglish (US)
Article number18
JournalACM Transactions on Reconfigurable Technology and Systems
Issue number4
StatePublished - Dec 2013


  • Analytical modeling
  • Homogeneous
  • Static power

ASJC Scopus subject areas

  • General Computer Science


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