TY - GEN
T1 - An adaptable low density parity check (LDPC) engine for space based communication systems
AU - Striemer, Gregory M.
AU - Akoglu, Ali
PY - 2010
Y1 - 2010
N2 - Space communication systems are characterized by the severe limitations to the on-board computational power and the tight constraints of received signal strengths. Also, these systems observe degradation in signals caused by large propagation latencies, extreme distances traveled, as well as data corruption causing high biterror rates. LDPC codes provide powerful error correction capability where signal power is very low, making them an ideal candidate for space based applications. A hardware architecture that is configurable to dynamic changes in channel conditions is a necessity for error resilient communication systems. In this study we demonstrate the feasibility of designing an FPGA based adaptable LDPC decoder architecture that also matches the throughput demand of current space based communications requirements. We design an LDPC engine that is adaptable to three code rates by taking advantage of the partial reconfiguration technology and parallel nature of the FPGA architecture. We evaluate the tradeoff between the level of parallelism to exploit on the FPGA when implementing LDPC codes and resource demand for each code rate under the constraints of delivering a partially reconfigurable and adaptable solution. Based on the implementation using a Xilinx Virtex-5 FPGA, our design handles context switching between the codes on board in 92μs.
AB - Space communication systems are characterized by the severe limitations to the on-board computational power and the tight constraints of received signal strengths. Also, these systems observe degradation in signals caused by large propagation latencies, extreme distances traveled, as well as data corruption causing high biterror rates. LDPC codes provide powerful error correction capability where signal power is very low, making them an ideal candidate for space based applications. A hardware architecture that is configurable to dynamic changes in channel conditions is a necessity for error resilient communication systems. In this study we demonstrate the feasibility of designing an FPGA based adaptable LDPC decoder architecture that also matches the throughput demand of current space based communications requirements. We design an LDPC engine that is adaptable to three code rates by taking advantage of the partial reconfiguration technology and parallel nature of the FPGA architecture. We evaluate the tradeoff between the level of parallelism to exploit on the FPGA when implementing LDPC codes and resource demand for each code rate under the constraints of delivering a partially reconfigurable and adaptable solution. Based on the implementation using a Xilinx Virtex-5 FPGA, our design handles context switching between the codes on board in 92μs.
UR - http://www.scopus.com/inward/record.url?scp=77956946933&partnerID=8YFLogxK
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U2 - 10.1109/AHS.2010.5546275
DO - 10.1109/AHS.2010.5546275
M3 - Conference contribution
AN - SCOPUS:77956946933
SN - 9781424458875
T3 - 2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010
SP - 105
EP - 112
BT - 2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010
T2 - 2010 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2010
Y2 - 15 June 2010 through 18 June 2010
ER -