ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore Architectures

Keyphrases

• High-speed Networks 100%
• On-chip Router 100%
• Many-core Architecture 100%
• Heterogeneous multicore 100%
• Router 66%
• Network on chip 66%
• Network Latency 66%
• Execution Time 33%
• Latency 33%
• Energy Efficiency Improvement 33%
• Putting 33%
• Traffic Route 33%
• Supervised Learning 33%
• Traffic Analysis 33%
• Injection Port 33%
• Rodinia 33%
• Crossbar Switch 33%
• Latency Reduction 33%
• Throughput Improvement 33%
• Router Architecture 33%
• Latency-sensitive 33%
• CPU-GPU 33%
• Learning Engine 33%

Computer Science

• Networks on Chips 100%
• Performance Network 100%
• Network Latency 66%
• Execution Time 33%
• Energy Efficiency 33%
• Supervised Learning 33%
• Traffic Analysis 33%
• Latency Reduction 33%
• Router Architecture 33%
• Crossbar Switch 33%