Albireo: Energy-efficient acceleration of convolutional neural networks via silicon photonics

Kyle Shiflett, Avinash Karanth, Razvan Bunescu, Ahmed Louri

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

With the end of Dennard scaling, highly-parallel and specialized hardware accelerators have been proposed to improve the throughput and energy-efficiency of deep neural network (DNN) models for various applications. However, collective data movement primitives such as multicast and broadcast that are required for multiply-and-accumulate (MAC) computation in DNN models are expensive, and require excessive energy and latency when implemented with electrical networks. This consequently limits the scalability and performance of electronic hardware accelerators. Emerging technology such as silicon photonics can inherently provide efficient implementation of multicast and broadcast operations, making photonics more amenable to exploit parallelism within DNN models. Moreover, when coupled with other unique features such as low energy consumption, high channel capacity with wavelength-division multiplexing (WDM), and high speed, silicon photonics could potentially provide a viable technology for scaling DNN acceleration.In this paper, we propose Albireo, an analog photonic architecture for scaling DNN acceleration. By characterizing photonic devices such as microring resonators (MRRs) and Mach-Zehnder modulators (MZM) using photonic simulators, we develop realistic device models and outline their capability for system level acceleration. Using the device models, we develop an efficient broadcast combined with multicast data distribution by leveraging parameter sharing through unique WDM dot product processing. We evaluate the energy and throughput performance of Albireo on DNN models such as ResNet18, MobileNet and VGG16. When compared to cur-rent state-of-the-art electronic accelerators, Albireo increases throughput by 110 X, and improves energy-delay product (EDP) by an average of 74 X with current photonic devices. Furthermore, by considering moderate and aggressive photonic scaling, the proposed Albireo design shows that EDP can be reduced by at least 229 X.

Original languageEnglish (US)
Title of host publicationProceedings - 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture, ISCA 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages860-873
Number of pages14
ISBN (Electronic)9781665433334
DOIs
StatePublished - Jun 2021
Event48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021 - Virtual, Online, Spain
Duration: Jun 14 2021Jun 19 2021

Publication series

NameProceedings - International Symposium on Computer Architecture
Volume2021-June
ISSN (Print)1063-6897

Conference

Conference48th ACM/IEEE Annual International Symposium on Computer Architecture, ISCA 2021
Country/TerritorySpain
CityVirtual, Online
Period6/14/216/19/21

Keywords

  • Deep neural networks
  • Hardware acceleration
  • Optical computing
  • Silicon photonics

ASJC Scopus subject areas

  • Hardware and Architecture

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