TY - GEN
T1 - Adaptive inter-router links for low-power, area-efficient and reliable network-on-chip(NoC) architectures
AU - Kodi, Avinash Karanth
AU - Sarathy, Ashwini
AU - Louri, Ahmed
AU - Wang, Janet
PY - 2009
Y1 - 2009
N2 - The increasing wire delay constraints in deep sub- micron VLSI designs have led to the emergence of scalable and modular Network-on-Chip(NoC) architectures. As the power consumption, area overhead and performance of the entire NoC is influenced by the router buffers, research efforts have targeted optimized router buffer design. In this paper, we propose iDEAL - inter-router, dual-function energy and area-efficient links capable of data transmission as well as data storage when required. iDEAL enables a reduction in the router buffer size by controlling the repeaters along the links to adaptively function as link buffers during congestion, thereby achieving nearly 30% savings in overall network power and 35% reduction in area with only a marginal 1- 3% drop in performance. In addition, aggressive speculative flow control further improves the performance of iDEAL. Moreover, the significant reduction in power consumption and area provides sufficient headroom for monitoring Negative Bias Temperature Instability(NBTI) effects in order to improve circuit reliability at reduced feature sizes.
AB - The increasing wire delay constraints in deep sub- micron VLSI designs have led to the emergence of scalable and modular Network-on-Chip(NoC) architectures. As the power consumption, area overhead and performance of the entire NoC is influenced by the router buffers, research efforts have targeted optimized router buffer design. In this paper, we propose iDEAL - inter-router, dual-function energy and area-efficient links capable of data transmission as well as data storage when required. iDEAL enables a reduction in the router buffer size by controlling the repeaters along the links to adaptively function as link buffers during congestion, thereby achieving nearly 30% savings in overall network power and 35% reduction in area with only a marginal 1- 3% drop in performance. In addition, aggressive speculative flow control further improves the performance of iDEAL. Moreover, the significant reduction in power consumption and area provides sufficient headroom for monitoring Negative Bias Temperature Instability(NBTI) effects in order to improve circuit reliability at reduced feature sizes.
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U2 - 10.1109/ASPDAC.2009.4796432
DO - 10.1109/ASPDAC.2009.4796432
M3 - Conference contribution
AN - SCOPUS:64549110241
SN - 9781424427482
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 1
EP - 6
BT - Proceedings of the ASP-DAC 2009
T2 - Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
Y2 - 19 January 2009 through 22 January 2009
ER -