A systematic construction of capacity-achieving irregular low-density parity-check codes

S. Sankaranarayan; Bane V Vasic; E. Kurtas

doi:10.1109/INTMAG.2003.1230516

A systematic construction of capacity-achieving irregular low-density parity-check codes

S. Sankaranarayan, Bane V Vasic, E. Kurtas

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

In this paper, we propose symmetric method to split column and rows of parity-check matrix (H^reg) of regular LDPC code in order to construct capacity-achieving irregular LDPC code with a given distribution (Λ^req, Ω^req).

Original language	English (US)
Title of host publication	Intermag 2003 - Program of the 2003 IEEE International Magnetics Conference
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	0780376471, 9780780376472
DOIs	https://doi.org/10.1109/INTMAG.2003.1230516
State	Published - 2003
Event	2003 IEEE International Magnetics Conference, Intermag 2003 - Boston, United States Duration: Mar 30 2003 → Apr 3 2003

Publication series

Name	Intermag 2003 - Program of the 2003 IEEE International Magnetics Conference

Other

Other	2003 IEEE International Magnetics Conference, Intermag 2003
Country/Territory	United States
City	Boston
Period	3/30/03 → 4/3/03

Keywords

Cyclic redundancy check
Equations
Magnetic recording
Optimization methods
Parity check codes
Partitioning algorithms

ASJC Scopus subject areas

General Engineering

Access to Document

10.1109/INTMAG.2003.1230516

Cite this

Sankaranarayan, S., Vasic, B. V., & Kurtas, E. (2003). A systematic construction of capacity-achieving irregular low-density parity-check codes. In Intermag 2003 - Program of the 2003 IEEE International Magnetics Conference Article 1230516 (Intermag 2003 - Program of the 2003 IEEE International Magnetics Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/INTMAG.2003.1230516

A systematic construction of capacity-achieving irregular low-density parity-check codes. / Sankaranarayan, S.; Vasic, Bane V; Kurtas, E.
Intermag 2003 - Program of the 2003 IEEE International Magnetics Conference. Institute of Electrical and Electronics Engineers Inc., 2003. 1230516 (Intermag 2003 - Program of the 2003 IEEE International Magnetics Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sankaranarayan, S, Vasic, BV & Kurtas, E 2003, A systematic construction of capacity-achieving irregular low-density parity-check codes. in Intermag 2003 - Program of the 2003 IEEE International Magnetics Conference., 1230516, Intermag 2003 - Program of the 2003 IEEE International Magnetics Conference, Institute of Electrical and Electronics Engineers Inc., 2003 IEEE International Magnetics Conference, Intermag 2003, Boston, United States, 3/30/03. https://doi.org/10.1109/INTMAG.2003.1230516

Sankaranarayan S, Vasic BV, Kurtas E. A systematic construction of capacity-achieving irregular low-density parity-check codes. In Intermag 2003 - Program of the 2003 IEEE International Magnetics Conference. Institute of Electrical and Electronics Engineers Inc. 2003. 1230516. (Intermag 2003 - Program of the 2003 IEEE International Magnetics Conference). doi: 10.1109/INTMAG.2003.1230516

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keywords = "Cyclic redundancy check, Equations, Magnetic recording, Optimization methods, Parity check codes, Partitioning algorithms",

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KW - Optimization methods

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A systematic construction of capacity-achieving irregular low-density parity-check codes

Abstract

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Keywords

ASJC Scopus subject areas

Access to Document

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