Abstract
Current CMOS technology is reaching its scaling limits and thus the CMOS based devices are slowly being replaced by new nanotechnology devices. These nanotechnology devices, however, pose some simulation challenges due to their non-monotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance of the simulator. This paper proposes a new circuit simulation approach that can effectively simulate nanotechnology devices, avoiding such problems. The experimental results show a 20-30 times speedup comparing with existing simulators.
Original language | English (US) |
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Article number | 1465138 |
Pages (from-to) | 2518-2521 |
Number of pages | 4 |
Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
DOIs | |
State | Published - 2005 |
Event | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: May 23 2005 → May 26 2005 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering