A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems

Pavan Poluri, Ahmed Louri

Research output: Contribution to journalArticlepeer-review

17 Scopus citations


Network-on-Chip (NoC) paradigm is rapidly evolving into an efficient interconnection network to handle the strict communication requirements between the increasing number of cores on a single chip. Diminishing transistor size is making the NoC increasingly vulnerable to both hard faults and soft errors. This paper concentrates on soft errors in NoCs. A soft error in an NoC router results in significant consequences such as data corruption, packet retransmission and deadlock among others. To this end, we propose Soft Error T olerant NoC Router (STNR) architecture, that is capable of detecting and recovering from soft errors occurring in different control stages of the routing pipeline. STNR exploits the use of idle cycles inherent in NoC packet routing pipeline to perform time redundant executions necessary for soft error tolerance. In doing so, STNR is able to detect and correct all single transient faults in the control stages of the pipeline. Simulation results using PARSEC and SPLASH-2 benchmarks show that STNR is able to accomplish such high level of soft error protection with a minimal impact on latency (an increase of 1.7 and 1.6 percent respectively). Additionally, STNR incurs an area overhead of 7 percent and power overhead of 13 percent as compared to the baseline unprotected router.

Original languageEnglish (US)
Article number6912980
Pages (from-to)107-110
Number of pages4
JournalIEEE Computer Architecture Letters
Issue number2
StatePublished - Jul 1 2015


  • Network-on-chip
  • performance
  • reliability
  • soft error

ASJC Scopus subject areas

  • Hardware and Architecture


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