TY - GEN
T1 - A radiation-hardened-by-design phase-locked loop using feedback voltage controlled oscillator
AU - Jung, Seok Min
AU - Roveda, Janet Meiling
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/4/13
Y1 - 2015/4/13
N2 - This paper presents a radiation-hardened-by-design (RHBD) phase-locked loop (PLL) which utilizes a feedback voltage controlled oscillator (FBVCO) to mitigate a single event transient (SET) strike. Whenever the SET pulse attacks the input control voltage of VCO, VCO gives rise to a frequency disturbance and PLL produces a huge jitter at the output clock. The proposed FBVCO consists of an open loop VCO, an integrator and a switched-capacitor resistor. The input transfer function of the FBVCO has a low-pass characteristic so that the FBVCO can reduce any perturbation at the input control voltage. In addition, the proposed RHBD PLL reduces size by using one loop filter (LF) and charge pump (CP) compared to prior works. We simulate the proposed scheme in 130 nm low power CMOS technology at 1.5V supply. The output frequency variation of the proposed PLL from the SET strike is 75% smaller than that of previous PLL at 300 MHz. This RHBD PLL consumes 6.2 mW at 400 MHz output frequency.
AB - This paper presents a radiation-hardened-by-design (RHBD) phase-locked loop (PLL) which utilizes a feedback voltage controlled oscillator (FBVCO) to mitigate a single event transient (SET) strike. Whenever the SET pulse attacks the input control voltage of VCO, VCO gives rise to a frequency disturbance and PLL produces a huge jitter at the output clock. The proposed FBVCO consists of an open loop VCO, an integrator and a switched-capacitor resistor. The input transfer function of the FBVCO has a low-pass characteristic so that the FBVCO can reduce any perturbation at the input control voltage. In addition, the proposed RHBD PLL reduces size by using one loop filter (LF) and charge pump (CP) compared to prior works. We simulate the proposed scheme in 130 nm low power CMOS technology at 1.5V supply. The output frequency variation of the proposed PLL from the SET strike is 75% smaller than that of previous PLL at 300 MHz. This RHBD PLL consumes 6.2 mW at 400 MHz output frequency.
KW - Phase-locked loop (PLL)
KW - loop filter (LF)
KW - radiation-hardened-by-design (RHBD)
KW - voltage controlled oscillator (VCO)
UR - http://www.scopus.com/inward/record.url?scp=84944315406&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84944315406&partnerID=8YFLogxK
U2 - 10.1109/ISQED.2015.7085407
DO - 10.1109/ISQED.2015.7085407
M3 - Conference contribution
AN - SCOPUS:84944315406
T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED
SP - 103
EP - 106
BT - Proceedings of the 16th International Symposium on Quality Electronic Design, ISQED 2015
PB - IEEE Computer Society
T2 - 16th International Symposium on Quality Electronic Design, ISQED 2015
Y2 - 2 March 2015 through 4 March 2015
ER -