TY - GEN
T1 - A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching
AU - Satish Kumar, Y.
AU - Li, Jun
AU - Talarico, Claudio
AU - Wang, Janet
PY - 2005
Y1 - 2005
N2 - Since the advent of new nanotechnologies, the variability of gate delay due to process variations has become a major concern. This paper proposes a new gate delay model that includes impact from both process variations and multiple input switching. The proposed model uses orthogonal polynomial based probabilistic collocation method to construct a delay analytical equation from circuit timing performance. From the experimental results, our approach has less that 0.2% error on the mean delay of gates and less than 3% error on the standard deviation.
AB - Since the advent of new nanotechnologies, the variability of gate delay due to process variations has become a major concern. This paper proposes a new gate delay model that includes impact from both process variations and multiple input switching. The proposed model uses orthogonal polynomial based probabilistic collocation method to construct a delay analytical equation from circuit timing performance. From the experimental results, our approach has less that 0.2% error on the mean delay of gates and less than 3% error on the standard deviation.
UR - http://www.scopus.com/inward/record.url?scp=33646939014&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=33646939014&partnerID=8YFLogxK
U2 - 10.1109/DATE.2005.31
DO - 10.1109/DATE.2005.31
M3 - Conference contribution
AN - SCOPUS:33646939014
SN - 0769522882
SN - 9780769522883
T3 - Proceedings -Design, Automation and Test in Europe, DATE '05
SP - 770
EP - 775
BT - Proceedings - Design, Automation and Test in Europe, DATE '05
T2 - Design, Automation and Test in Europe, DATE '05
Y2 - 7 March 2005 through 11 March 2005
ER -