TY - GEN
T1 - A power efficient reconfigurable system-in-stack
T2 - 27th IEEE International System on Chip Conference, SOCC 2014
AU - Gadfort, Peter
AU - Dasu, Aravind
AU - Akoglu, Ali
AU - Leow, Yoon Kah
AU - Fritze, Michael
N1 - Publisher Copyright:
© 2014 IEEE.
PY - 2014/11/5
Y1 - 2014/11/5
N2 - Increasing computing power efficiency has become more important as more applications are moving to mobile platforms, which tend to have a limited power available. Being able to perform a wide variety of computations efficiently is especially important for power constrained embedded applications such as unmanned aerial vehicles (UAVs), which may not be able to send the data out for processing and must perform some of the processing on-board. This paper describes a 3D FPGA-DRAM architecture that can not only deliver the necessary flexibility, by using FPGAs, but also provide the computing efficiency in the form of floating-point arithmetic accelerators that is required for UAVs. We examine the efficiency of this system in 65 nm, 90 nm, and 130 nm CMOS technologies and report simulation results showing a peak computing efficiency of 28.94 GFLOPs/W for a 4,096 point 1 dimensional FFT and 25.03 GFLOPs/W for a 1,024 point × 1,024 point 2 dimensional FFT.
AB - Increasing computing power efficiency has become more important as more applications are moving to mobile platforms, which tend to have a limited power available. Being able to perform a wide variety of computations efficiently is especially important for power constrained embedded applications such as unmanned aerial vehicles (UAVs), which may not be able to send the data out for processing and must perform some of the processing on-board. This paper describes a 3D FPGA-DRAM architecture that can not only deliver the necessary flexibility, by using FPGAs, but also provide the computing efficiency in the form of floating-point arithmetic accelerators that is required for UAVs. We examine the efficiency of this system in 65 nm, 90 nm, and 130 nm CMOS technologies and report simulation results showing a peak computing efficiency of 28.94 GFLOPs/W for a 4,096 point 1 dimensional FFT and 25.03 GFLOPs/W for a 1,024 point × 1,024 point 2 dimensional FFT.
UR - http://www.scopus.com/inward/record.url?scp=84911931198&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84911931198&partnerID=8YFLogxK
U2 - 10.1109/SOCC.2014.6948892
DO - 10.1109/SOCC.2014.6948892
M3 - Conference contribution
AN - SCOPUS:84911931198
T3 - International System on Chip Conference
SP - 11
EP - 16
BT - International System on Chip Conference
A2 - Shi, Kaijian
A2 - Buchner, Thomas
A2 - Zhao, Danella
A2 - Sridhar, Ramalingam
PB - IEEE Computer Society
Y2 - 2 September 2014 through 5 September 2014
ER -