Abstract
In the Deep Sub Micron (DSM) regime, due to non-uniform scaling of interconnects, coupling capacitance between wires becomes an increasingly dominant fraction of the total wire capacitance. Crosstalk causes delay variations on signal lines and raises signal integrity problems. Including crosstalk in timing analysis has become imperative for current technologies. The existing timing analysis methods do not consider gate driving capability, output loading effects and waveform shape, and hence are not always accurate. In this paper, we propose a non-iterative equivalent waveform model that addresses these issues.
Original language | English (US) |
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Article number | 1465125 |
Pages (from-to) | 2465-2468 |
Number of pages | 4 |
Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
DOIs | |
State | Published - 2005 |
Event | IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: May 23 2005 → May 26 2005 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering