A low jitter digital phase-locked loop with a hybrid analog/digital PI control

Seok Min Jung; Janet Meiling Roveda

doi:10.1109/NEWCAS.2015.7182019

A low jitter digital phase-locked loop with a hybrid analog/digital PI control

Seok Min Jung, Janet Meiling Roveda

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

3 Scopus citations

Abstract

This paper presents a novel digital phase-locked loop (DPLL) architecture with a hybrid analog/digital proportional/integral (PI) control to generate a low jitter output clock. The hybrid analog/digital PI control mitigates a time to digital converter (TDC) quantization noise and reduces the deterministic jitter (DJ). In addition, a digital phase accumulator (DPA) based high resolution digitally controlled oscillator (DCO) suppresses a DCO quantization error. To reduce a random jitter (RJ), we propose a closed loop voltage controlled oscillator (CLVCO) which can suppress the random noise of oscillator because of a negative feedback loop. We design the proposed DPLL architecture in 130 nm CMOS technology at 1.2V supply. The proposed low jitter DPLL shows 4.3 psec of the DJ and 12.5 psec of the RJ. This DPLL operates from 256 MHz to 1.024 GHz and consumes 4.1 mW at 1.024 GHz output frequency.

Original language	English (US)
Title of host publication	Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479988938
DOIs	https://doi.org/10.1109/NEWCAS.2015.7182019
State	Published - Aug 6 2015
Event	13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015 - Grenoble, France Duration: Jun 7 2015 → Jun 10 2015

Publication series

Name	Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015

Other

Other	13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015
Country/Territory	France
City	Grenoble
Period	6/7/15 → 6/10/15

Keywords

PI control
closed loop VCO (CLVCO)
deterministic jitter (DJ)
digital phase accumulator (DPA)
digital phase-locked loop (DPLL)
digitally controlled phase shift (DCPS)
random jitter (RJ)

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/NEWCAS.2015.7182019

Cite this

Jung, S. M., & Roveda, J. M. (2015). A low jitter digital phase-locked loop with a hybrid analog/digital PI control. In Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015 Article 7182019 (Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/NEWCAS.2015.7182019

A low jitter digital phase-locked loop with a hybrid analog/digital PI control. / Jung, Seok Min; Roveda, Janet Meiling.
Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7182019 (Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Jung, SM & Roveda, JM 2015, A low jitter digital phase-locked loop with a hybrid analog/digital PI control. in Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015., 7182019, Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, Institute of Electrical and Electronics Engineers Inc., 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, Grenoble, France, 6/7/15. https://doi.org/10.1109/NEWCAS.2015.7182019

Jung SM, Roveda JM. A low jitter digital phase-locked loop with a hybrid analog/digital PI control. In Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7182019. (Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015). doi: 10.1109/NEWCAS.2015.7182019

Jung, Seok Min ; Roveda, Janet Meiling. / A low jitter digital phase-locked loop with a hybrid analog/digital PI control. Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015).

@inproceedings{911eb4ebeaa54872a944561051a4d69a,

title = "A low jitter digital phase-locked loop with a hybrid analog/digital PI control",

abstract = "This paper presents a novel digital phase-locked loop (DPLL) architecture with a hybrid analog/digital proportional/integral (PI) control to generate a low jitter output clock. The hybrid analog/digital PI control mitigates a time to digital converter (TDC) quantization noise and reduces the deterministic jitter (DJ). In addition, a digital phase accumulator (DPA) based high resolution digitally controlled oscillator (DCO) suppresses a DCO quantization error. To reduce a random jitter (RJ), we propose a closed loop voltage controlled oscillator (CLVCO) which can suppress the random noise of oscillator because of a negative feedback loop. We design the proposed DPLL architecture in 130 nm CMOS technology at 1.2V supply. The proposed low jitter DPLL shows 4.3 psec of the DJ and 12.5 psec of the RJ. This DPLL operates from 256 MHz to 1.024 GHz and consumes 4.1 mW at 1.024 GHz output frequency.",

keywords = "PI control, closed loop VCO (CLVCO), deterministic jitter (DJ), digital phase accumulator (DPA), digital phase-locked loop (DPLL), digitally controlled phase shift (DCPS), random jitter (RJ)",

author = "Jung, {Seok Min} and Roveda, {Janet Meiling}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015 ; Conference date: 07-06-2015 Through 10-06-2015",

year = "2015",

month = aug,

day = "6",

doi = "10.1109/NEWCAS.2015.7182019",

language = "English (US)",

series = "Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015",

}

TY - GEN

T1 - A low jitter digital phase-locked loop with a hybrid analog/digital PI control

AU - Jung, Seok Min

AU - Roveda, Janet Meiling

PY - 2015/8/6

Y1 - 2015/8/6

N2 - This paper presents a novel digital phase-locked loop (DPLL) architecture with a hybrid analog/digital proportional/integral (PI) control to generate a low jitter output clock. The hybrid analog/digital PI control mitigates a time to digital converter (TDC) quantization noise and reduces the deterministic jitter (DJ). In addition, a digital phase accumulator (DPA) based high resolution digitally controlled oscillator (DCO) suppresses a DCO quantization error. To reduce a random jitter (RJ), we propose a closed loop voltage controlled oscillator (CLVCO) which can suppress the random noise of oscillator because of a negative feedback loop. We design the proposed DPLL architecture in 130 nm CMOS technology at 1.2V supply. The proposed low jitter DPLL shows 4.3 psec of the DJ and 12.5 psec of the RJ. This DPLL operates from 256 MHz to 1.024 GHz and consumes 4.1 mW at 1.024 GHz output frequency.

AB - This paper presents a novel digital phase-locked loop (DPLL) architecture with a hybrid analog/digital proportional/integral (PI) control to generate a low jitter output clock. The hybrid analog/digital PI control mitigates a time to digital converter (TDC) quantization noise and reduces the deterministic jitter (DJ). In addition, a digital phase accumulator (DPA) based high resolution digitally controlled oscillator (DCO) suppresses a DCO quantization error. To reduce a random jitter (RJ), we propose a closed loop voltage controlled oscillator (CLVCO) which can suppress the random noise of oscillator because of a negative feedback loop. We design the proposed DPLL architecture in 130 nm CMOS technology at 1.2V supply. The proposed low jitter DPLL shows 4.3 psec of the DJ and 12.5 psec of the RJ. This DPLL operates from 256 MHz to 1.024 GHz and consumes 4.1 mW at 1.024 GHz output frequency.

KW - PI control

KW - closed loop VCO (CLVCO)

KW - deterministic jitter (DJ)

KW - digital phase accumulator (DPA)

KW - digital phase-locked loop (DPLL)

KW - digitally controlled phase shift (DCPS)

KW - random jitter (RJ)

UR - http://www.scopus.com/inward/record.url?scp=84945156635&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84945156635&partnerID=8YFLogxK

U2 - 10.1109/NEWCAS.2015.7182019

DO - 10.1109/NEWCAS.2015.7182019

M3 - Conference contribution

AN - SCOPUS:84945156635

T3 - Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015

BT - Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015

Y2 - 7 June 2015 through 10 June 2015

ER -

A low jitter digital phase-locked loop with a hybrid analog/digital PI control

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