A hybrid processing element based reconfigurable architecture for hashing algorithms

Given the high computation demand for cryptography and hashing algorithms there is a need to develop flexible and high performance architectures. This paper proposes a methodology to derive processing elements as a starting point for the state-of-the-art reconfigurable computing and presents a case-study to show that application-specific reconfigurable computing has performance benefits close to fully-custom designs in addition to the intended reconfigurablity. We use hashing algorithms as a case study to propose a novel application-specific reconfigurable architecture based on a balanced mixture of coarse and fine grained processing elements with a tuned interconnect structure. For that purpose we introduce a methodology to derive hybrid grained processing elements and expose both fine and coarse grain parallelism based on a new common and recurring computation pattern extraction tool. After extracting the recurring patterns between SHA-1 and MD5 algorithms, we derive the unified interconnect architecture tailored to the control data dependencies of both the algorithms. That way the amount of reconfiguration on the proposed architecture when switching between the two algorithms is minimized. The proposed reconfigurable architecture is synthesized using the Synopsys design compiler targeted at TSMC 250 nm libraries. We compare its performance with ASIC technology on SHA-1 and MD5 algorithms. Results show that the proposed architecture which is reconfigurable between the two hashing algorithms has frequency of operation close to ASIC implementation of the individual algorithms for iterative and pipelined versions and results with 35% savings in area.