A hybrid FPGA model to estimate on-chip crossbar logic utilization in soc platforms

FPGA analytical models, that express the relationship between architectural parameters (e.g., LUT size, cluster size, inputs per cluster, etc) and performance (e.g., logic utilization, critical path delay, power, etc), have been designed mainly for island-style FPGAs targeting a general application. Therefore, most analytical models will produce inaccurate results when heterogeneous FPGA architectures are targeted. Furthermore, the inherent continuous nature of mathematical models also prevent them from capturing the discrete effects of uniform circuits. Example of such circuits are crossbar switches and barrel shifters. In this paper, we derive a biased model that captures the discrete effects with respect to the logic utilization of crossbar switches by varying the LUT size.